HIGH-PER.ORMANCE PRODUCTS
Description
The SK10/100EL15W is a low skew 1:4 clock distribution
chips designed explicitly for low skew clock distribution
applications. This device is fully compatible with
MC10EL15 & MC100EL15. The device can be driven by
either a differential or single-ended ECL or, if positive power
supplies are used, PECL input signal. If a single-ended
input is to be used, the VBB output should be connected
to the CLK* input and bypassed to VCC via a 0.01 µF
capacitor. The EL15W provides a VBB output for either
single-ended use or as a DC bias for AC coupling to the
device. The VBB pin should be used only as a bias for
EL15W as its current sink/source capability is limited.
Whenever used, the VBB pin should be bypassed to VCC
via a 0.01 µF capacitor.
The EL15W features a multiplexed clock input to allow for
the distribution of a lower speed scan or test clock along
with the high speed system clock. When LOW (or left
open and pulled LOW by the input pull-down resistor) the
SEL pin will select the differential clock input.
The common enable (EN*) is synchronous so that the
outputs will only be enabled/disabled when they are already
in the LOW state. This avoids any chance of generating a
runt clock pulse when the device is enabled/disabled as
can happen with an asynchronous control. The internal
flip-flop is clocked on the falling edge of the input clock,
therefore, all associated specification limits are referenced
to the negative edge of the clock input.
SK10/100EL15W
1:4 Clock
Distribution
.eatures
•
Extended Supply Voltage Range: (VEE = –5.5V to
–3.0V, VCC = 0V) or (VCC = + 3.0V to +5.5V,
VEE=0V)
50 ps Output-to-Output Skew
Synchronous Enable/Disable
Multiplexed Clock Input
75KΩ Internal Input Pull-Down Resistors
Fully Compatible with MC10EL15 and
MC100EL15
Specified Over Industrial Temperature Range:
–40
o
C to +85
o
C
ESD Protection of >4000V
Available in 16-Pin SOIC Package
•
•
•
•
•
•
•
•
PIN Description
Pin Name
CLK
SCLK
EN*
SEL
V
BB
Q0Q3, Q0*-Q3*
.unction
Differential Clock Inputs
Synchronous Clock Input
Synchronous Enable
Clock Select Input
Reference Output Voltage
Differential Clock Outputs
.unctional Block Diagram
Q0
1
16
VCC
EN*
CLK
L
H
X
X
X
SCLK
X
X
L
H
X
SEL
L
L
H
H
X
EN*
L
L
L
L
H
Q
L
H
L
H
L*
Q0*
2
Q
D
15
Q1
3
1
14
SCLK
Q1*
4
0
13
CLK
Q2
5
12
CLK*
Q2*
6
11
VBB
Q3
7
10
SEL
*On next negative transition of CLK or SCLK.
Truth Table
1
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Q3*
8
9
VEE
Revision 1/February 12, 2001
SK10/100EL15W
HIGH-PER.ORMANCE PRODUCTS
Package Information
16 Pin SOIC Package
–A–
0.25 (0.010) M
B
S
16
9
–B
P
8 PL
1
8
R
x 45
˚
G
C
SEATING
PLANE
D 168 PL
0.25 (0.010)
M
T
B
S
A S
K
MILLIMETERS
DIM
A
B
C
D
.
G
J
K
M
P
R
MIN
9/80
3.80
1.35
0.35
0.40
MAX
10.00
4.00
1.75
0.49
1.25
INCHES
MIN
0.386
0.150
0.054
0.014
0.016
MAX
0.393
0.157
0.068
0.019
0.049
1.27 BSC
0.19
0.10
0
o
5.80
0.25
0.25
0.25
7
o
6.20
0.50
0.050 BSC
0.008
0.004
0
o
0.229
0.010
0.009
0.009
7
o
0.244
0.019
NOTES:
1. Dimensioning and tolerancing per ANSI Y14.5M,
1982.
2. Controlling dimension: millimeter.
3. Dimensions A and B do not include mold protrusion.
4. Maximum mold protrusion 0.150 (0.006) per side.
5. Dimension D does not include Dambar protrusion.
Allowable Dambar protrusion shall be 0.13 (0.005)
total in excess of d dimension at maximum material
condition.
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Revision 1/February 12, 2001
J
F
–
T
–
M
SK10/100EL15W
HIGH-PER.ORMANCE PRODUCTS
DC Characteristics
SK10/100EL15W DC Electrical Characteristics (Notes 1, 2)
(V
CC –
V
EE
= +3.0V to +5.5V ; V
OUT
loaded 50Ω to V
CC
– 2.0V)
TA = –40
o
C
TA = 0
o
C
TA = +25
o
C
TA = +85
o
C
S y mb o l
I
IN
Ch a r a c t e r i s t i c
I nput Cur r ent ( Di f f )
( SE)
Power Supply Cur rent
10EL
100EL
Output Reference Voltage
5
10EL
100EL
Power Supply Voltage
Mi n
- 150
Typ
Ma x
150
150
35
35
Mi n
- 150
Typ
Ma x
150
150
36
36
Mi n
- 150
Typ
Ma x
150
150
36
38
Mi n
- 150
Typ
Ma x
150
150
38
41
1. 19
1. 26
5. 5
Un i t
µA
µA
mA
mA
mV
mV
V
I
EE
20
21
1. 43
1. 38
3. 0
21
21
21
22
22
24
V
BB
V
CC
V
EE
1. 30 1. 38
1. 26 1. 38
5. 5
3. 0
1. 27 1. 35
1. 26 1. 38
5. 5
3. 0
1. 25 1. 31
1. 26 1. 38
5. 5
3. 0
AC Characteristics
SK10/100EL15W AC Electrical Characteristics
(V
CC –
V
EE
= +3.0V to +5.5V ; V
OUT
loaded 50Ω to V
CC
– 2.0V)
TA = –40
o
C
TA = 0
o
C
TA = +25
o
C
TA = +85
o
C
Symbol Characteristic
t
PLH
t
P HL
t
skew
t
S
t
H
V
PP
V
C MR
t
r
, t
f
Propagation Delay
CL K t o Q ( Di f f )
CLK t o Q ( SE)
SCLK t o Q
Par t-to-Par t Skew
Within-Device SkeW
S e t u p T i me E N *
H o l d T i me E N *
Mi n i mu m I n p u t S w i n g C L K
3
C o mmo n Mo d e R a n g e C L K
4
V P P < 5 0 0 mV
V P P > 5 0 0 mV
Min
560
470
465
Max
650
710
685
200
50
Min
580
500
495
Max
675
695
700
200
50
Min
591
510
510
Max
695
680
705
200
50
Min
620
545
566
Max
740
725
745
200
50
Un i t
ps
ps
ps
ps
ps
ps
ps
150
400
250
1000
150
400
250
VEE + 1. 3
VEE + 1. 5
205
1000
VCC 0. 4
VCC 0. 4
350
150
400
250
1000
150
400
250
1000
VCC 0. 4
VCC 0. 4
380
mV
V
V
ps
VEE + 1. 3 VCC 0. 4
VEE + 1. 5 VCC 0. 4
195
340
VEE + 1. 3 VCC 0. 4 VEE + 1. 3
VEE + 1. 5 VCC 0. 4 VEE + 1. 5
210
360
225
Output Rise/.all Times
Qn , Qn * ( 2 0 % t o 8 0 %)
Revision 1/February 12, 2001
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SK10/100EL15W
HIGH-PER.ORMANCE PRODUCTS
AC Characteristics
(continued)
Notes:
1. 10EL circuits are designed to meet the DC specifications shown in the table after thermal equilibrium
has been established. The circuit is in a test socket or mounted on a printed circuit board and
transverse airflow greater than 500 lfpm is maintained. Outputs are terminated through a 50Ω resistor
to VCC –2.0V.
2. 100K circuits are designed to meet the DC specification shown in the table where transverse airflow
greater than 500 lfpm is maintained.
3. Minimum input swing for which AC parameters guaranteed.
4. CMR range is referenced to the most positive side of the differential input signal. Normal operation is
obtained if the high level falls within the specified range and the peak-to-peak voltage lies between
VPP
(min)
and 1V. The lower end of the CMR range varies 1:1 with VEE and is equal to VEE + 1.3V for
VPP < 500 mV and VEE + 1.5V for VPP > 500 mV.
5. Voltages referenced to VCC = 0V (ECL mode).
6.
For standard ECL DC specifications, refer to the ECL Logic Family Standard DC Specifications Data
Sheet.
7. For part ordering descriptions, see HPP Part Ordering Information Data Sheet.
Ordering Information
Ordering Code
SK10EL15WD
SK10EL15WDT
SK100EL15WD
SK100EL15WDT
SK10EL15WU
SK100EL15WU
Package ID
16-SOIC
16-SOIC
16-SOIC
16-SOIC
Die
Die
Temperature Range
Industrial
Industrial
Industrial
Industrial
Contact Information
Division Headquarters
10021 Willow Creek Road
San Diego, CA 92131
Phone: (858) 695-1808
FAX: (858) 695-2633
Semtech Corporation
High-Performance Products Division
Marketing Group
1111 Comstock Street
Santa Clara, CA 95054
Phone: (408) 566-8776
FAX: (408) 727-8994
Revision 1/February 12, 2001
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