S29AL008J
8-Mbit (1M × 8-Bit/512K × 16-Bit), 3 V,
Boot Sector Flash
Distinctive Characteristics
Architectural Advantages
Single Power Supply Operation
– Full voltage range: 2.7 to 3.6 volt read and write operations for
battery-powered applications
Manufactured on 110 nm Process Technology
– Fully compatible with 200 nm S29AL008D
Secured Silicon Sector region
– 128-word/256-byte sector for permanent, secure identification
through an 8-word/16-byte random Electronic Serial Number
accessible through a command sequence
– May be programmed and locked at the factory or by the customer
Flexible Sector Architecture
– One 16 Kbyte, two 8 Kbyte, one 32 Kbyte, and fifteen 64 Kbyte
sectors (byte mode)
– One 8 Kword, two 4 Kword, one 16 Kword, and fifteen 32 Kword
sectors (word mode)
Sector Group Protection Features
– A hardware method of locking a sector to prevent any program or
erase operations within that sector
– Sectors can be locked in-system or via programming equipment
– Temporary Sector Unprotect feature allows code changes in
previously locked sectors
Unlock Bypass Program Command
– Reduces overall programming time when issuing multiple program
command sequences
Top or Bottom Boot Block Configurations Available
Compatibility with JEDEC standards
– Pinout and software compatible with single-power supply Flash
– Superior inadvertent write protection
Performance Characteristics
High Performance
– Access times as fast as 55 ns
– Extended temperature range (–40°C to +125°C)
– Automotive AEC-Q100 Grade 3 (–40 °C to +85 °C)
– Automotive AEC-Q100 Grade 1 (–40 °C to +125 °C)
Ultra Low Power Consumption (typical values at 5 MHz)
– 0.2 µA Automatic Sleep mode current
– 0.2 µA standby mode current
– 7 mA read current
– 20 mA program/erase current
Cycling Endurance: 1,000,000 cycles per sector typical
Data Retention: 20 years typical
Package Options
48-ball Fine-pitch BGA
48-pin TSOP
Software Features
CFI (Common Flash Interface) Compliant
– Provides device-specific information to the system, allowing host
software to easily reconfigure for different Flash devices
Erase Suspend/Erase Resume
– Suspends an erase operation to read data from, or program data
to, a sector that is not being erased, then resumes the erase
operation
Data# Polling and Toggle Bits
– Provides a software method of detecting program or erase
operation completion
Hardware Features
Ready/Busy# Pin (RY/BY#)
– Provides a hardware method of detecting program or erase cycle
completion
Hardware Reset Pin (RESET#)
– Hardware method to reset the device to reading array data
WP# input pin
– For boot sector devices: at V
IL
, protects first or last 16 Kbyte
sector depending on boot configuration (top boot or bottom boot)
Cypress Semiconductor Corporation
Document Number: 002-00778 Rev. *M
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised June 09, 2017
S29AL008J
General Description
The S29AL008J is a 8 Mbit, 3.0 Volt-only Flash memory organized as 1,048,576 bytes or 524,288 words. The device is offered in
48-ball Fine-pitch BGA (0.8 mm pitch), and 48-pin TSOP packages. The word-wide data (x16) appears on DQ15–DQ0; the byte-
wide (x8) data appears on DQ7–DQ0. This device is designed to be programmed in-system with the standard system 3.0 volt V
CC
supply. A 12.0 V V
PP
or 5.0 V
CC
are not required for write or erase operations. The device can also be programmed in standard
EPROM programmers.
The device offers access times of up to 55 ns allowing high speed microprocessors to operate without wait states. To eliminate bus
contention the device has separate chip enable (CE#), write enable (WE#) and output enable (OE#) controls.
The device requires only a
single 3.0 volt power supply
for both read and write functions. Internally generated and regulated
voltages are provided for the program and erase operations.
The S29AL008J is entirely command set compatible with the
JEDEC single-power-supply Flash standard.
Commands are written
to the command register using standard microprocessor write timings. Register contents serve as input to an internal state-machine
that controls the erase and programming circuitry. Write cycles also internally latch addresses and data needed for the programming
and erase operations. Reading data out of the device is similar to reading from other Flash or EPROM devices.
Device programming occurs by executing the program command sequence. This initiates the
Embedded Program
algorithm—an
internal algorithm that automatically times the program pulse widths and verifies proper cell margin. The
Unlock Bypass
mode
facilitates faster programming times by requiring only two write cycles to program data instead of four.
Device erasure occurs by executing the erase command sequence. This initiates the
Embedded Erase
algorithm—an internal
algorithm that automatically preprograms the array (if it is not already programmed) before executing the erase operation. During
erase, the device automatically times the erase pulse widths and verifies proper cell margin.
The host system can detect whether a program or erase operation is complete by observing the RY/BY# pin, or by reading the DQ7
(Data# Polling) and DQ6 (toggle)
status bits.
After a program or erase cycle has been completed, the device is ready to read array
data or accept another command.
The
sector erase architecture
allows memory sectors to be erased and reprogrammed without affecting the data contents of other
sectors. The device is fully erased when shipped from the factory.
Hardware data protection
measures include a low V
CC
detector that automatically inhibits write operations during power
transitions. The
hardware sector protection
feature disables both program and erase operations in any combination of the sectors
of memory. This can be achieved in-system or via programming equipment.
The
Erase Suspend/Erase Resume
feature enables the user to put erase on hold for any period of time to read data from, or
program data to, any sector that is not selected for erasure. True background erase can thus be achieved.
The
hardware RESET# pin
terminates any operation in progress and resets the internal state machine to reading array data. The
RESET# pin may be tied to the system reset circuitry. A system reset would thus also reset the device, enabling the system
microprocessor to read the boot-up firmware from the Flash memory.
The device offers two power-saving features. When addresses have been stable for a specified amount of time, the device enters
the
automatic sleep mode.
The system can also place the device into the
standby mode.
Power consumption is greatly reduced in
both these modes.
Cypress Flash technology combines years of Flash memory manufacturing experience to produce the highest levels of quality,
reliability and cost effectiveness. The device electrically erases all bits within a sector simultaneously via Fowler-Nordheim
tunneling. The data is programmed using hot electron injection.
Document Number: 002-00778 Rev. *M
Page 2 of 50
S29AL008J
Contents
Distinctive Characteristics
.................................................. 1
General Description
............................................................. 2
1.
2.
3.
3.1
4.
5.
6.
6.1
7.
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
7.9
7.10
7.11
8.
8.1
8.2
Product Selector Guide
............................................... 4
Block Diagram..............................................................
4
Connection Diagrams..................................................
5
Special Handling Instructions......................................... 6
Pin Configuration.........................................................
6
Logic Symbol
............................................................... 6
Ordering Information
................................................... 7
S29AL008J Standard Products...................................... 7
Device Bus Operations................................................
9
Word/Byte Configuration................................................ 9
Requirements for Reading Array Data........................... 9
Writing Commands/Command Sequences.................. 10
Program and Erase Operation Status.......................... 10
Standby Mode.............................................................. 10
Automatic Sleep Mode................................................. 10
RESET#: Hardware Reset Pin..................................... 11
Output Disable Mode ................................................... 12
Autoselect Mode .......................................................... 13
Sector Group Protection/Unprotection ......................... 14
Temporary Sector Group Unprotect............................. 15
Secured Silicon Sector Flash Memory Region
....... 17
Factory Locked: Secured Silicon Sector Programmed
and Protected at the Factory........................................ 17
Customer Lockable: Secured Silicon Sector NOT Pro-
grammed
or Protected at the Factory .......................................... 17
Common Flash Memory Interface (CFI)
................... 18
Hardware Data Protection............................................ 21
11.7 DQ3: Sector Erase Timer.............................................. 32
12.
13.
Absolute Maximum Ratings.......................................
33
Operating Ranges
....................................................... 33
14. DC Characteristics......................................................
34
14.1 CMOS Compatible ........................................................ 34
15.
16.
17.
17.1
17.2
17.3
17.4
17.5
17.6
18.
19.
Test Conditions
........................................................... 35
Key to Switching Waveforms.....................................
35
AC Characteristics......................................................
36
Read Operations........................................................... 36
Hardware Reset (RESET#)........................................... 37
Word/Byte Configuration (BYTE#) ................................ 38
Erase/Program Operations ........................................... 39
Temporary Sector Group Unprotect.............................. 42
Alternate CE# Controlled Erase/Program Operations .. 43
Erase and Programming Performance
..................... 44
TSOP and BGA Pin Capacitance
............................... 45
20. Physical Dimensions
.................................................. 46
20.1 48-Pin Standard TSOP ................................................. 46
20.2 48-Ball Fine-Pitch Ball Grid Array (BGA)
8.15 mm x 6.15 mm ...................................................... 47
21.
Revision History..........................................................
48
9.
9.1
10.
10.1
10.2
10.3
10.4
Command Definitions................................................
22
Reading Array Data ..................................................... 22
Reset Command .......................................................... 22
Autoselect Command Sequence ................................. 22
Enter Secured Silicon Sector/Exit Secured Silicon Sector
Command Sequence ................................................... 23
10.5 Word/Byte Program Command Sequence................... 23
10.6 Unlock Bypass Command Sequence .......................... 23
10.7 Chip Erase Command Sequence ................................ 24
10.8 Sector Erase Command Sequence ............................. 25
10.9 Erase Suspend/Erase Resume Commands ................ 25
10.10Command Definitions Table ........................................ 26
11.
11.1
11.2
11.3
11.4
11.5
11.6
Write Operation Status
..............................................
DQ7: Data# Polling ......................................................
RY/BY#: Ready/Busy#.................................................
DQ6: Toggle Bit I .........................................................
DQ2: Toggle Bit II ........................................................
Reading Toggle Bits DQ6/DQ2....................................
DQ5: Exceeded Timing Limits .....................................
28
28
29
30
30
31
32
Page 3 of 50
Document Number: 002-00778 Rev. *M
S29AL008J
1.
Product Selector Guide
Family Part Number
Speed Option
Voltage Range: V
CC
= 2.7-3.6 V
V
CC
= 3.0-3.6 V
Max access time, ns (t
ACC
)
Max CE# access time, ns (t
CE
)
Max CE# access time, ns (t
OE
)
Note
See AC Characteristics
on page 36
for full specifications.
55
55
55
30
70
70
30
S29AL008J
70
2. Block Diagram
RY/BY#
V
CC
V
SS
RESET#
Sector Switches
Erase Voltage
Generator
DQ0–DQ15 (A-1)
Input/Output
Buffers
WE#
BYTE#
WP#
State
Control
Command
Register
PGM Voltage
Generator
Chip Enable
Output Enable
Logic
Data
Latch
CE#
OE#
Y-Decoder
Y-Gating
V
CC
Detector
Timer
Address Latch
X-Decoder
Cell Matrix
A0–A18
Document Number: 002-00778 Rev. *M
Page 3 of 50
S29AL008J
3.
Connection Diagrams
Figure 3.1
48-pin Standard TSOP (TS048)
A15
A14
A13
A12
A11
A10
A9
A8
NC
NC
WE#
RESET#
NC
WP#
RY/BY#
A18
A17
A7
A6
A5
A4
A3
A2
A1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
A16
BYTE#
V
SS
DQ15/A-1
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
V
CC
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
OE#
V
SS
CE#
A0
Figure 3.2
48-ball Fine-pitch BGA (VBK048)
(Top View, Balls Facing Down)
A6
A13
A5
A9
A4
WE#
A3
RY/BY#
A2
A7
A1
A3
B6
A12
B5
A8
B4
RESET#
B3
WP#
B2
A17
B1
A4
C6
A14
C5
A10
C4
NC
C3
A18
C2
A6
C1
A2
D6
A15
D5
A11
D4
NC
D3
NC
D2
A5
D1
A1
E6
A16
E5
DQ7
E4
DQ5
E3
DQ2
E2
DQ0
E1
A0
F6
G6
H6
V
SS
H5
DQ6
H4
DQ4
H3
DQ3
H2
DQ1
H1
V
SS
BYTE# DQ15/A-1
F5
DQ14
F4
DQ12
F3
DQ10
F2
DQ8
F1
CE#
G5
DQ13
G4
V
CC
G3
DQ11
G2
DQ9
G1
OE#
Document Number: 002-00778 Rev. *M
Page 4 of 50
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