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IS46DR32160C-5BBLA1

Description
DDR DRAM, 16MX32, 0.6ns, CMOS, PBGA126, 10. 50 X 13.50 MM, 1.20 MM HEIGHT, 0.80 MM PITCH, LEAD FREE, TWBGA-126
Categorystorage    storage   
File Size911KB,44 Pages
ManufacturerISSI(Integrated Silicon Solution Inc.)
Websitehttp://www.issi.com/
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IS46DR32160C-5BBLA1 Overview

DDR DRAM, 16MX32, 0.6ns, CMOS, PBGA126, 10. 50 X 13.50 MM, 1.20 MM HEIGHT, 0.80 MM PITCH, LEAD FREE, TWBGA-126

IS46DR32160C-5BBLA1 Parametric

Parameter NameAttribute value
Objectid1207932810
Parts packaging codeBGA
package instructionTFBGA,
Contacts126
Reach Compliance Codecompliant
ECCN codeEAR99
access modeFOUR BANK PAGE BURST
Maximum access time0.6 ns
Other featuresAUTO/SELF REFRESH
JESD-30 codeR-PBGA-B126
length13.5 mm
memory density536870912 bit
Memory IC TypeDDR DRAM
memory width32
Number of functions1
Number of ports1
Number of terminals126
word count16777216 words
character code16000000
Operating modeSYNCHRONOUS
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
organize16MX32
Package body materialPLASTIC/EPOXY
encapsulated codeTFBGA
Package shapeRECTANGULAR
Package formGRID ARRAY, THIN PROFILE, FINE PITCH
Maximum seat height1.2 mm
self refreshYES
Maximum supply voltage (Vsup)1.9 V
Minimum supply voltage (Vsup)1.7 V
Nominal supply voltage (Vsup)1.8 V
surface mountYES
technologyCMOS
Temperature levelINDUSTRIAL
Terminal formBALL
Terminal pitch0.8 mm
Terminal locationBOTTOM
width10.5 mm
IS43/46DR32160C
16Mx32    
   
512Mb DDR2 DRAM
FEATURES
• V
dd
= 1.8V ±0.1V, V
ddq
= 1.8V ±0.1V
• JEDEC standard 1.8V I/O (SSTL_18-compatible)
• Double data rate interface: two data transfers
per clock cycle
• Differential data strobe (DQS, DQS)
• 4-bit prefetch architecture
• On chip DLL to align DQ and DQS transitions
with CK
• 4 internal banks for concurrent operation
• Programmable CAS latency (CL) 3, 4, 5, and 6
supported
• Posted CAS and programmable additive latency
(AL) 0, 1, 2, 3, 4, and 5 supported
• WRITE latency = READ latency - 1 tCK
• Programmable burst lengths: 4 or 8
• Adjustable data-output drive strength, full and
reduced strength options
• On-die termination (ODT)
ADVANCED INFORMATION
JUNE 2012
ISSI's 512Mb DDR2 SDRAM uses a double-data-rate
architecture to achieve high-speed operation. The
double-data rate architecture is essentially a 4n-prefetch
architecture, with an interface designed to transfer two
data words per clock cycle at the I/O balls.
The 512Mb DDR2 SDRAM is provided in a wide bus
x32 format, designed to offer a smaller footprint and
support compact designs.
DESCRIPTION
ADDRESS TABLE
Parameter
Configuration
Refresh Count
Row Addressing
Column
Addressing
Bank Addressing
Precharge
Addressing
16M x 32
4M x 32 x 4 banks
8K/64ms
A0-A12
A0-A8
BA0, BA1
A10/AP
OPTIONS 
• Configuration:
16M x 32 (IS43/46DR32160C - 8K refresh)
• Package: x32: 126-ball WBGA
• Timing – Cycle time
2.5ns @CL=6, DDR2-800E
3.0ns @CL=5, DDR2-667D
3.75ns @CL=4, DDR2-533C
5.0ns @CL=3, DDR2-400B
• Temperature Range:
Commercial (0°C ≤ Tc ≤ 85°C; 0°C ≤ T
a
≤ 70°C)
Industrial (–40°C ≤ Tc ≤ 95°C; –40°C ≤ T
a
≤ 85°C)
Automotive, A1 (–40°C ≤ Tc ≤ 95°C; –40°C ≤ T
a
≤ 85°C)
Automotive, A2 (–40°C ≤ Tc ≤ 105°C; –40°C ≤ T
a
≤ 105°C)
KEY TIMING PARAMETERS
Speed Grade
tRCD
tRP
tRC
tRAS
tCK @CL=3
tCK @CL=4
tCK @CL=5
tCK @CL=6
-25E
15
15
60
45
5
3.75
3
2.5
-3D
15
15
60
45
5
3.75
3
3
-37C
15
15
60
45
5
3.75
3.75
3.75
-5B
15
15
55
40
5
5
5
5
Tc = Case Temp, T
a
= Ambient Temp
Copyright © 2012 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without
notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the lat-
est version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reason-
ably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications
unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances
Integrated Silicon Solution, Inc. — www.issi.com
Rev.  00B
06/07/2012
1

IS46DR32160C-5BBLA1 Related Products

IS46DR32160C-5BBLA1 IS43DR32160C-5BBL
Description DDR DRAM, 16MX32, 0.6ns, CMOS, PBGA126, 10. 50 X 13.50 MM, 1.20 MM HEIGHT, 0.80 MM PITCH, LEAD FREE, TWBGA-126 DDR DRAM, 16MX32, 0.6ns, CMOS, PBGA126, 10. 50 X 13.50 MM, 1.20 MM HEIGHT, 0.80 MM PITCH, LEAD FREE, TWBGA-126
Objectid 1207932810 1207932766
Parts packaging code BGA BGA
package instruction TFBGA, TFBGA,
Contacts 126 126
Reach Compliance Code compliant compliant
ECCN code EAR99 EAR99
access mode FOUR BANK PAGE BURST FOUR BANK PAGE BURST
Maximum access time 0.6 ns 0.6 ns
Other features AUTO/SELF REFRESH AUTO/SELF REFRESH
JESD-30 code R-PBGA-B126 R-PBGA-B126
length 13.5 mm 13.5 mm
memory density 536870912 bit 536870912 bit
Memory IC Type DDR DRAM DDR DRAM
memory width 32 32
Number of functions 1 1
Number of ports 1 1
Number of terminals 126 126
word count 16777216 words 16777216 words
character code 16000000 16000000
Operating mode SYNCHRONOUS SYNCHRONOUS
Maximum operating temperature 85 °C 70 °C
organize 16MX32 16MX32
Package body material PLASTIC/EPOXY PLASTIC/EPOXY
encapsulated code TFBGA TFBGA
Package shape RECTANGULAR RECTANGULAR
Package form GRID ARRAY, THIN PROFILE, FINE PITCH GRID ARRAY, THIN PROFILE, FINE PITCH
Maximum seat height 1.2 mm 1.2 mm
self refresh YES YES
Maximum supply voltage (Vsup) 1.9 V 1.9 V
Minimum supply voltage (Vsup) 1.7 V 1.7 V
Nominal supply voltage (Vsup) 1.8 V 1.8 V
surface mount YES YES
technology CMOS CMOS
Temperature level INDUSTRIAL COMMERCIAL
Terminal form BALL BALL
Terminal pitch 0.8 mm 0.8 mm
Terminal location BOTTOM BOTTOM
width 10.5 mm 10.5 mm
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