Integrated
Circuit
Systems, Inc.
Product Data Sheet
M2025/26
VCSO B
ASED
C
LOCK
PLL
WITH
A
UTO
S
WITCH
P
IN
A
SSIGNMENT
(9 x 9 mm SMT)
FIN_SEL1
GND
P_SEL2
DIF_REF0
nDIF_REF0
REF_SEL
DIF_REF1
nDIF_REF1
VCC
FIN_SEL0
MR_SEL1
MR_SEL0
LOL
NBW
VCC
DNC
DNC
DNC
27
26
25
24
23
22
21
20
19
G
ENERAL
D
ESCRIPTION
The M2025/26 is a VCSO (Voltage Controlled SAW
Oscillator) based clock jitter
attenuator PLL designed for clock
jitter attenuation and frequency
translation. The device is ideal for
generating the transmit reference
clock for optical network systems
supporting 2.5-10 GB data rates.
It can serve to jitter attenuate a stratum reference clock
or a recovered clock in loop timing mode. The
M2025/26 module includes a proprietary SAW (surface
acoustic wave) delay line as part of the VCSO. This
results in a high frequency, high-Q, low phase noise
oscillator that assures low intrinsic output jitter.
28
29
30
31
32
33
34
35
36
M2025
M2026
(Top View)
18
17
16
15
14
13
12
11
10
P_SEL1
P_SEL0
nFOUT
FOUT
GND
REF_ACK
AUTO
VCC
GND
F
EATURES
◆
Integrated SAW (surface acoustic wave) delay line;
low phase jitter of < 0.5ps rms, typical (12kHz to 20MHz
or 50kHz to 80MHz)
◆
Output frequencies of 15 to 700 MHz
*
◆
LVPECL clock output (CML and LVDS options available)
◆
Reference clock inputs support differential LVDS,
LVPECL, as well as single-ended LVCMOS, LVTTL
◆
Loss of Lock (LOL) output pin; Narrow Bandwidth
control input (NBW pin)
◆
AutoSwitch (AUTO pin) - automatic (non-revertive)
reference clock reselection upon clock failure
◆
Acknowledge pin (REF_ACK pin) indicates the actively
selected reference input
◆
Options for Hitless Switching (HS) with or without
Phase Build-out (PBO) to enable SONET (GR-253) /SDH
(G.813) MTIE and TDEV compliance during reselection
◆
Single 3.3V power supply
◆
Small 9 x 9 mm SMT (surface mount) package
Figure 1: Pin Assignment
Example I/O Clock Frequency Combinations
Using
M2025-11-622.0800 or M2026-11-622.0800
Input Reference
Clock
(MHz)
(M2025)
(M2026)
GND
GND
GND
OP_IN
nOP_OUT
nVC
VC
OP_OUT
nOP_IN
1
2
3
4
5
6
7
8
9
PLL Ratio
(Pin Selectable)
(M2025)
(M2026)
Output Clock
(MHz)
19.44 or 38.88
77.76
155.52
622.08
32 or 16
8
4
1
622.08
Table 1: Example I/O Clock Frequency Combinations
* Specify VCSO center frequency at time of order.
S
IMPLIFIED
B
LOCK
D
IAGRAM
M2025/26
NBW
MUX
PLL
Phase
Detector
Loop Filter
DIF_REF0
nDIF_REF0
DIF_REF1
nDIF_REF1
REF_ACK
REF_SEL
AUTO
Auto
Ref Sel
0
R Div
(1, 4,
16, 64)
VCSO
1
M Divider
0
1
LOL Phase
Detector
Mfin Divider
(1, 4, 8, 32
or
1, 4, 8, 16)
(1, 4, 16, 64)
LOL
P Divider
(1, 4, 8, 32 or TriState)
Tri-state
FOUT
nFOUT
MR_SEL1:0
FIN_SEL1:0
P_SEL2:0
2
2
3
M / R Divider
LUT
Mfin Divider
LUT
P Divider
LUT
Figure 2: Simplified Block Diagram
M2025/26 Datasheet Rev 1.0
M2025/26 VCSO Based Clock PLL with AutoSwitch
Revised 30Jul2004
●
I n t e g r a t e d C i r c u i t S y s t e m s, I n c .
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M2025/26
VCSO B
ASED
C
LOCK
PLL
WITH
A
UTO
S
WITCH
Product Data Sheet
P
IN
D
ESCRIPTIONS
Number
1, 2, 3, 10, 14, 26
4
9
5
8
6
7
11, 19, 33
12
Name
GND
OP_IN
nOP_IN
nOP_OUT
OP_OUT
nVC
VC
VCC
AUTO
I/O
Configuration
Description
Ground
Input
Output
Input
Power
Input
Power supply ground connections.
External loop filter connections.
See Figure 5, External Loop Filter, on pg. 8.
Power supply connection, connect to +
3.3
V.
Automatic/manual reselection mode for clock input:
Internal pull-down resistor
1
Logic
1
automatic reselection upon clock failure
(non-revertive)
Logic
0
manual selection only (using
REF_SEL)
Reference Acknowledgement pin for input mux state; outputs
the currently selected reference input pair. Can also be used
to control an external clock switch.
Logic
1
indicates
nDIF_REF1, DIF_REF1
Logic
0
indicates
nDIF_REF0, DIF_REF0
No internal terminator
Clock output pair. Differential LVPECL.
13
REF_ACK
Output
15
16
17
18
25
20
21
22
23
24
27
28
29
30
31
FOUT
nFOUT
P_SEL1
P_SEL0
P_SEL2
nDIF_REF1
DIF_REF1
REF_SEL
nDIF_REF0
DIF_REF0
FIN_SEL1
FIN_SEL0
MR_SEL0
MR_SEL1
LOL
Output
Input
Input
Input
Input
Input
Input
P divider selection. LVCMOS/LVTTL.
Internal pull-down resistor
1
Post-PLL , 5, P Divider Look-Up Table (LUT), on pg. 3.
See Table
Reference clock input pair 1. Differential LVPECL or LVDS.
Resistor bias on inverting terminal supports TTL or LVCMOS.
Internal pull-down resistor
1
Reference clock input selection. LVCMOS/LVTTL:
Internal pull-down resistor
1
Logic
1
selects
DIF_REF1, nDIF_REF1.
Logic
0
selects
DIF_REF0, nDIF_REF0
.
Biased to Vcc/2
2
Internal pull-down resistor
1
Reference clock input pair 0. Differential LVPECL or LVDS.
Resistor bias on inverting terminal supports TTL or LVCMOS.
Biased to Vcc/2
2
I
nput clock frequency selection. LVCMOS/LVTTL.
Internal pull-down resistor
1
See Table
3,
Mfin Divider Look-Up Table (LUT) on pg. 3.
M and R divider value selection. LVCMOS/ LVTTL.
Internal pull-UP resistor
1
See Table 4, M and R Divider Look-Up Table (LUT) on pg. 3.
Output
32
34, 35, 36
NBW
DNC
Input
Internal pull-UP resistor
1
Do Not Connect.
Loss of Lock indicator output. Asserted when internal PLL is
not tracking the input reference for frequency and phase.
3
Logic
1
indicates loss of lock.
Logic
0
indicates locked condition.
Narrow Bandwidth enable. LVCMOS/LVTTL:
Logic
1
- Narrow loop bandwidth
, R
IN
= 2100kΩ
.
Logic
0
- Wide bandwidth
, R
IN
= 100kΩ
.
Table 2: Pin Descriptions
Note 1: For typical values of internal pull-down and pull-UP resistors, see
DC Characteristics
on pg. 10.
Note 2: Biased toVcc/2, with 50kΩ to Vcc and 50kΩ to ground. See
Differential Inputs Biased to VCC/2
on pg. 10.
Note 3: See
LVCMOS Outputs
in
DC Characteristics
on pg. 10.
M2025/26 Datasheet Rev 1.0
I n t e g r a t e d C i r c u i t S y s t e m s, I n c .
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M2025/26
VCSO B
ASED
C
LOCK
PLL
WITH
A
UTO
S
WITCH
Product Data Sheet
D
ETAILED
B
LOCK
D
IAGRAM
R
LOOP
C
LOOP
R
POST
C
POST
C
POST
R
LOOP
C
LOOP
OP_OUT
R
POST
nOP_OUT
nVC
VC
External
Loop Filter
Components
M2025/26
OP_IN
nOP_IN
NBW
MUX
PLL
Phase
Detector
DIF_REF0
nDIF_REF0
DIF_REF1
nDIF_REF1
REF_ACK
REF_SEL
AUTO
Auto
Ref Sel
R
IN
0
R Div
(1, 4,
16, 64)
R
IN
1
M Div
(1, 4,16, 64)
LOL
Phase
Detector
Loop Filter
Amplifier
Mfin Divider
(1, 4, 8, 32) or
(1, 4, 8, 16)
Phase
Locked
Loop
(PLL)
SAW Delay Line
Phase
Shifter
VCSO
0
1
LOL
M / R Divider
LUT
Mfin Divider
LUT
P Divider
LUT
MR_SEL1:0
FIN_SEL1:0
P_SEL2:0
2
2
3
P Divider
(1, 4, 8, 32,
TriState)
CML or PECL
Options
FOUT
nFOUT
Figure 3: Detailed Block Diagram
D
IVIDER
S
ELECTION
T
ABLES
Mfin Divider Look-Up Table (LUT)
The
FIN_SEL1:0
pins select the Mfin divider value, which
establishes the PLL clock multiplication ratio. Since the
VCSO frequency is fixed, this allows input reference
selection.
FIN_SEL1:0
P Divider Look-Up Table (LUT)
The
P_SEL2:0
pins select the P divider values, which set
the output clock frequency. A P divider of value of
1
will
provide a
622.08MHz
output when using a
622.08MHz
VCSO, for example. P divider values of
4
,
8
, or
32
are
also available, plus a TriState mode. The output can be
placed into the valid states as listed in Table 5.
P_SEL2:0
Mfin Value
(M2025) (M2026)
Input Ref. Freq. (MHz)
1
M2025-yz-622.0800 or M2026-yz-622.0800
0
0
1
1
0
1
0
1
32 or 16
8
4
1
19.44 or 38.88
77.76
155.52
622.08
P Value
for
FOUT
32
32
1
4
8
4
8
Tri-state
M2025-yz-622.0800 or M2026-yz-622.0800
Output Frequency (MHz)
FOUT
Table 3: Mfin Divider Look-Up Table (LUT)
Note 1: Example with
M2025-yz-622.0800 or M2026-yz-622.0800
M and R Divider Look-Up Table (LUT)
The
MR_SEL1:0
pins select the M and R divider values,
which establish phase detector frequency. A lower
phase detector frequency improves jitter tolerance and
lowers loop bandwidth.
MR_SEL1:0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
19.44
19.44
622.08
155.52
77.76
155.52
77.76
N/A
Table 5: P Divider Look-Up Table (LUT)
M
1
4
16
64
R
1
4
16
64
Description
0
0
1
1
0
1
1
0
1
Four sets of divider values to enable
adjustment of bandwidth and jitter
tolerance
Note 1: Do not use with
FIN_SEL1:0=11;
Maximum Phase Detector
Frequency=175MHz
Table 4: M and R Divider Look-Up Table (LUT)
M2025/26 Datasheet Rev 1.0
I n t e g r a t e d C i r c u i t S y s t e m s, I n c .
●
3 of 12
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Revised 30Jul2004
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Integrated
Circuit
Systems, Inc.
General Guidelines for M and R Divider Selection
M2025/26
VCSO B
ASED
C
LOCK
PLL
WITH
A
UTO
S
WITCH
Product Data Sheet
Input Reference Clocks
Two clock reference inputs and a selection mux are
provided. Either reference clock input can accept a
differential clock signal (such as LVPECL or LVDS) or
a single-ended clock input (LVCMOS or LVTTL on the
non-inverting input).
A single-ended reference clock on the unselected
reference input can cause an increase in output
clock jitter. For this reason, differential reference
inputs are preferred; interference from a differential
input on the non-selected input is minimal.
•
A lower phase detector frequency should be used for
loop timing applications to assure PLL tracking,
especially during GR-253 jitter tolerance testing. The
recommended maximum phase detector frequency
for loop timing mode is
19.44MHz
.
When
LOL
is to be used for system health monitoring,
the phase detector frequency should be
5MHz
or
greater. Low phase detector frequencies make
LOL
overly sensitive, and higher phase detector
frequencies make
LOL
less sensitive. The
LOL
pin
should not be used during loop timing mode.
The preceding guideline also applies when using the
AutoSwitch Mode, since AutoSwitch uses the
LOL
output for clock fault detection.
•
•
F
UNCTIONAL
D
ESCRIPTION
The M2025/26 is a PLL (Phase Locked Loop) based
clock generator that generates output clocks synchro-
nized to one of two selectable input reference clocks.
An internal high "Q" SAW delay line provides low jitter
signal performance and establishes the output
frequency of the VCSO (Voltage Controlled SAW
Oscillator). In a given M2025/26 device, the VCSO
center frequency is fixed. A common center frequency
is
622.08MHz,
for SONET for SDH optical network
applications. The VCSO center frequency is specified at
time of order (see “Ordering Information” on pg. 12).
The VCSO has a guaranteed tuning range of
±120
ppm
(commercial temperature grade).
Pin selectable dividers are used within the PLL and
for the output clock. This enables tailoring of device
functionality and performance. The Mfin divider controls
the overall PLL multiplication ratio and thus determines
the input reference clock (see Table 3, on pg. 3). The
M and R dividers control the phase detector frequency
(see Table 4). The P divider scales the VCSO output
enabling lower output frequency selections (Table 5).
The M2025/26 includes a Loss of Lock (
LOL
) indicator,
which provides status information to system
management software. A Narrow Bandwidth (
NBW
)
control pin is provided as an additional mechanism for
adjusting PLL loop bandwidth without affecting the
phase detector frequency.
Options are available for Hitless Switching (HS) with or
without Phase Build-out (PBO). They provide
SONET/SDH MTIE and TDEV compliance during a
reference clock reselection.
Allowance for a single-ended input has been facilitated
by a unique input resistor bias scheme, which is
described next and shown in Figure 4.
M2025/26 Datasheet Rev 1.0
I n t e g r a t e d C i r c u i t S y s t e m s, I n c .
●
Configuration of a single-ended input has been
facilitated by biasing
nDIF_REF0
and
nDEF_REF1
to Vcc/2,
with 50kΩ to Vcc and 50kΩ to ground. The input clock
structure, and how it is used with either
LVCMOS/LVTTL inputs or a DC- coupled LVPECL
clock, is shown in Figure 4.
DIF_REF0
50k
Ω
VCC
50k
Ω
X
50k
Ω
MUX
LVCMOS/
LVTTL
nDIF_REF0
VCC
0
DIF_REF1
LVPECL
127
Ω
VCC
127
Ω
VCC
50k
Ω
1
82
Ω
50k
Ω
nDIF_REF1
REF_SEL
82
Ω
50k
Ω
M2025/26
Figure 4: Input Reference Clocks
Differential Inputs
Differential LVPECL inputs are connected to both
reference input pins in the usual manner. The external
load termination resistors shown in Figure 4 (the 127Ω
and 82Ω resistors) is ideally suited for both AC and DC
coupled LVPECL reference clock lines. These provide
the 50Ω load termination and the V
TT
bias voltage.
Single-ended Inputs
Single-ended inputs (LVCMOS or LVTTL) are
connected to the non-inverting reference input pin
(
DIF_REF0
or
DIF_REF1
). The inverting reference input pin
(
nDIF_REF0
or
nDIF_REF1
) must be left unconnected.
In single-ended operation, when the unused inverting
input pin (nDIF_REF0 or
nDEF_REF1)
is left floating (not
connected), the input will self-bias at VCC/2.
PLL Operation
The M2025/26 is a complete clock PLL. It uses a phase
detector and configurable dividers to synchronize the
output of the VCSO with the selected reference clock.
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The M2025/26 components are similar to the M2020/21
components except that the M2025/26 includes the
selectable AutoSwitch feature. The M2025/26 also has
only one clock output, as the AutoSwitch control pins
replace of the second output.
The PLL will work correctly, meaning it will phase-lock
the VCSO output to the input reference clock, when the
internal phase detector inputs are able to run at the
same frequency. This means the PLL dividers must be
set appropriately and a suitable reference frequency
must be chosen for the intended output frequency.
When the PLL is not set up appropriately, the VCSO is
forced to its upper or lower operating limit which is
typically about 250 ppm above or below the VCSO
center frequency (no more than 500 ppm above or
below).
In normal phase-locked condition, the instantaneous
phase error is measured by the phase detector and is
converted to charge pump current pulses. These
current pulses are then integrated by the external loop
filter to create a VCSO control voltage. The loop filter
acts as a low pass filter to remove unwanted reference
clock jitter above a determined frequency or PLL
bandwidth. For reference phase jitter frequencies within
the loop bandwidth, phase jitter amplitude is passed on
to the output clock according to the PLL loop frequency
response curve.
The relationship between the nominal VCSO center
frequency (Fvcso), the M divider, and the input
reference frequency (Fin) is:
-
Fvcso
=
Fin
×
Mfin
×
---
R
Example Frequency and Divider Combinations
Using M2026-yz-622.0800
Fvcso
=
Fin
38.88
77.76
155.52
622.08
x
Mfin
x
M/R
16 x (1/1, 4/4, etc.)
8 x (1/1, 4/4, etc.)
4 x (1/1, 4/4, etc.)
1 x (1/1, 4/4, etc.)
M
M2025/26
VCSO B
ASED
C
LOCK
PLL
WITH
A
UTO
S
WITCH
Product Data Sheet
The
P_SEL2:0
pins select the value for the P divider. (See
Table 5 on pg. 3.)
Accounting for the P divider, the complete relationship
between the input clock reference frequency (Fin) and
output clock frequency (Fout) is defined as:
M
×
Mfin
Fvcso
-
Fout
=
-------------------
=
Fin
×
-------------------------
Due to the narrow tuning range of the VCSO (+120ppm
guaranteed), appropriate selection of all of the following
are required for the PLL be able to lock: VCSO center
frequency, input frequency, and divider selections.
TriState
The TriState feature puts the LVPECL output driver into
a high impedance state, effectively disconnecting the
driver from the
FOUT
and
nFOUT
pins of the device. A
logic
0
is then present on the clock net. The impedance
of the clock net is then set to 50Ω by the external circuit
resistors. (This is in distinction to a CMOS output in
TriState, in which case the net goes to a high
impedance and the logic value floats.) The 50Ω
impedance level of the LVPECL TriState allows
manufacturing In-circuit Test to drive the clock net with
an external 50Ω generator to validate the integrity of
clock net and the clock load.
Any unused output (single-ended or differential) should
be left unconnected (floating) in system application.
This minimizes output switching current and therefore
minimizes noise modulation of the VCSO.
P
R
×
P
622.08
Loss of Lock Indicator (LOL) Output Pin
Under normal device operation, when the PLL is locked,
the LOL Phase Detector drives
LOL
to logic
0
. Under
circumstances when the VCSO cannot fully phase lock
to the input (as measured by a greater than 4 ns
discrepancy between the feedback and reference clock
rising edges at the LOL Phase Detector) the
LOL
output
goes to logic 1. The
LOL
pin will return back to logic
0
when the phase detector error is less than 2 ns. The
loss of lock indicator is a low current LVCMOS output.
Guidelines for Using LOL
Table 6: Example I/O Clock Frequency Combinations
The M, R, and Mfin dividers can be set by pin configura-
tion using the input pins
MR_SEL1
,
MR_SEL0
,
FIN_SEL1
, and
FIN_SEL0
.
Post-PLL Divider
The M2025/26 also features a post-PLL (P) divider.
Through use of the P divider, the device’s output
frequency (Fout) can be that of the VCSO (such as
622.08MHz
) or the VCSO frequency divided by
4
,
8
or
32
(common optical reference clocks in SONET and SDH
systems).
M2025/26 Datasheet Rev 1.0
I n t e g r a t e d C i r c u i t S y s t e m s, I n c .
●
In a given application, the magnitude of peak-to-peak
jitter at the phase detector will usually increase as the R
divider is increased. If the
LOL
pin will be used to detect
an unusual clock condition, or a clock fault, the
MR_SEL1:0
pins should be set to provide a phase detector
frequency of
5MHz
or greater (the phase detector
frequency is equal to Fin divided by the R divider).
Otherwise, false
LOL
indications may result. A phase
detector frequency of
10MHz
or greater is desirable
when reference jitter is over
500ps
, or when the device is
used within a noisy system environment.
LOL
should not
be used when the device is used in a loop timing
application.
Revised 30Jul2004
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