Low common-mode output voltage (part identification DAC1653D)
•
High common-mode output voltage (part identification DAC1658D)
An optional on-chip digital modulator converts the complex I/Q pattern from baseband to IF. The mixer frequency is set by
writing to the Serial Peripheral Interface (SPI) control registers associated with the on-chip 40-bit Numerically Controlled
Oscillator (NCO). This accurately places the IF carrier in the frequency domain. The 13-bit phase adjustment feature, the
12-bit digital gain and the 16-bit digital offset enable full control of the analog output signals.
The DAC165xD is fully compatible with device subclass 1 of the JEDEC JESD204B standard, guaranteeing deterministic
and repeatable interface latency using the differential SYSREF signal. The device also supports harmonic clocking to
reduce system-level clock synthesis and distribution challenges.
Multiple Device Synchronization (MDS) enables multiple DAC channels to be sample synchronous and phase coherent to
within one DAC clock period. MDS is ideal for LTE and LTE-A MIMO transceiver applications.
The DAC165xD includes a
2, 4
or
8
divider to achieve the best possible noise performance at the analog outputs,
allowing harmonic clocking through the system. The internal regulator adjusts the full-scale output current between 10 mA
and 30 mA.
The device is available in a VFQFP-N 56 package (8 mm
8 mm).
2013, Integrated Device Technology, Inc. (IDT) and its subsidiaries reserves the right to change the detail specifications as may be required to permit improvements in the design of its product.
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