DAC1653D/DAC1658D
®
Dual 16-bit DAC: 10 Gbps JESD204B interface:
x2, x4 and x8 interpolating
Datasheet
Revision 2.41
1. G
ENERAL DESCRIPTION
DAC1653D and DAC1658D are high-speed, high-performance 16-bit dual channel Digital-to-Analog Converters (DACs).
The devices provide sample rates up to 2 Gsps with selectable
2, 4
and
8
interpolation filters optimized for multi-carrier
and broadband wireless transmitters.
When both devices are referred to in this data sheet, the following convention will be used: DAC165xD.
The DAC165xD integrates a JEDEC JESD204B compatible high-speed serial input data interface running up to 10 Gbps
allowing dual channel input sampling at up to 1 Gsps over four differential lanes. It offers numerous advantages over
traditional parallel digital interfaces:
•
•
•
•
•
•
•
•
•
Easier Printed-Circuit Board (PCB) layout
Lower radiated noise
Lower pin count
Self-synchronous link
Skew compensation
Deterministic latency
Multiple Device Synchronization (MDS); JESD204B subclass 1 compatible
Harmonic clocking support
Assured FPGA interoperability
There are two versions of the DAC165xD:
•
Low common-mode output voltage (part identification DAC1653D)
•
High common-mode output voltage (part identification DAC1658D)
An optional on-chip digital modulator converts the complex I/Q pattern from baseband to IF. The mixer frequency is set by
writing to the Serial Peripheral Interface (SPI) control registers associated with the on-chip 40-bit Numerically Controlled
Oscillator (NCO). This accurately places the IF carrier in the frequency domain. The 13-bit phase adjustment feature, the
12-bit digital gain and the 16-bit digital offset enable full control of the analog output signals.
The DAC165xD is fully compatible with device subclass 1 of the JEDEC JESD204B standard, guaranteeing deterministic
and repeatable interface latency using the differential SYSREF signal. The device also supports harmonic clocking to
reduce system-level clock synthesis and distribution challenges.
Multiple Device Synchronization (MDS) enables multiple DAC channels to be sample synchronous and phase coherent to
within one DAC clock period. MDS is ideal for LTE and LTE-A MIMO transceiver applications.
The DAC165xD includes a
2, 4
or
8
divider to achieve the best possible noise performance at the analog outputs,
allowing harmonic clocking through the system. The internal regulator adjusts the full-scale output current between 10 mA
and 30 mA.
The device is available in a VFQFP-N 56 package (8 mm
8 mm).
2013, Integrated Device Technology, Inc. (IDT) and its subsidiaries reserves the right to change the detail specifications as may be required to permit improvements in the design of its product.
DAC1653D/DAC1658D
Dual 16-bit DAC: 10 Gbps JESD204B interface: x2, x4 and x8 interpolating
Datasheet
2. F
EATURES AND BENEFITS
Dual channel 16-bit resolution
SFDR
RBW
= 88 dBc typical (f
s
= 1.50 Gsps;
interpolation
2;
bandwidth = 250 MHz; f
out
= 150 MHz)
NSD =
167
dBc/Hz typical (f
o
= 70 MHz)
IMD3 = 85 dBc typical (f
s
= 1.50 Gsps; interpolation
2;
f
o1
= 152 MHz; f
o2
= 155.1 MHz)
2.0 GSps maximum output update rate
JEDEC JESD204B device subclass I compatible:
SYSREF based deterministic and repeatable interface
latency
Multiple device synchronization enables multiple DAC
Four carriers ACLR = 76 dB typical (f
s
= 1.50 Gsps;
channels to be sample synchronous and phase coherent
f
NCO
= 350 MHz)
to within one DAC clock period
1, 2 or 4 configurable JESD204B serial input lanes
RF enable/disable pin and RF automatic mute
running up to 10 Gbps with embedded termination and
programmable equalization gain (CTLE)
1 Gsps maximum baseband input data rate
Clock divider by 2, 4, 6 and 8 available at the input of the
clock path
SPI interface (3-wire or 4-wire mode) for control setting
Group delay compensation
and status monitoring
Differential scalable output current from 10 mA to 30 mA
Analog offset control (10-bit auxiliary DACs)
Embedded NCO with 40-bit programmable frequency
Power-down mode controls
and 16-bit phase adjustment
Embedded complex (IQ) digital modulator
On-chip 0.7 V reference
1.2 V and 3.3 V power supplies (for DAC1653D series,
Industrial temperature range
40 C
to +85
C
the 3.3V supply voltage can be lowered to 2.7V for lower
power consumption)
Flexible SPI power supply (1.8 V or 1.2 V) ensuring
Low (DAC1653D) or high (DAC1658D) common-mode
compatibility with on-board SPI bus
output voltage
Flexible differential SYNC signals power supply (1.8 V or
VFQFP-N 56 package (8 mm
8 mm)
1.2 V) ensuring compatibility with on-board devices
Embedded Temperature Sensor
Embedded Power On Reset
Configurable IOs pins for monitoring, interrupt
Lane swapping and polarity swapping
XBERT features (PRBS31, 23, 15, 7, JTSPAT, STLTP)
Signal Power Detector, IQ-Range detector, Level
detectors with Auto-Mute feature
3. A
PPLICATIONS
Wireless infrastructure radio base station transceivers, including: LTE-A, LTE, MC-GSM, W-CDMA, TD-SCDMA
LMDS/MMDS, point-to-point microwave backhaul
Direct Digital Synthesis (DDS) instruments
High-definition video broadcast production equipment
Automated Test Equipment (ATE)
DAC1653D; DAC1658D
© IDT 2014. All rights reserved.
Datasheet
Rev. 2.41 — 28 April 2014
2 of 168
DAC1653D/DAC1658D
Dual 16-bit DAC: 10 Gbps JESD204B interface: x2, x4 and x8 interpolating
Datasheet
4. O
RDERING INFORMATION
Table 1.
Ordering information
Package
Name
DAC1653D2G0NLGA8
DAC1653D1G5NLGA8
DAC1653D1G0NLGA8
DAC1658D2G0NLGA8
DAC1658D1G5NLGA8
DAC1658D1G0NLGA8
DAC1653D2G0NLGA
DAC1653D1G5NLGA
DAC1653D1G0NLGA
DAC1658D2G0NLGA
DAC1658D1G5NLGA
DAC1658D1G0NLGA
VFQFP-N 56
VFQFP-N 56
VFQFP-N 56
VFQFP-N 56
VFQFP-N 56
VFQFP-N 56
VFQFP-N 56
VFQFP-N 56
VFQFP-N 56
VFQFP-N 56
VFQFP-N 56
VFQFP-N 56
Description
VFQFP-N 8.0
8.0
0.85 mm; no lead
VFQFP-N 8.0
8.0
0.85 mm; no lead
VFQFP-N 8.0
8.0
0.85 mm; no lead
VFQFP-N 8.0
8.0
0.85 mm; no lead
VFQFP-N 8.0
8.0
0.85 mm; no lead
VFQFP-N 8.0
8.0
0.85 mm; no lead
VFQFP-N 8.0
8.0
0.85 mm; no lead
VFQFP-N 8.0
8.0
0.85 mm; no lead
VFQFP-N 8.0
8.0
0.85 mm; no lead
VFQFP-N 8.0
8.0
0.85 mm; no lead
VFQFP-N 8.0
8.0
0.85 mm; no lead
VFQFP-N 8.0
8.0
0.85 mm; no lead
Shipping Packaging
Tape & Reel
Tape & Reel
Tape & Reel
Tape & Reel
Tape & Reel
Tape & Reel
Tray
Tray
Tray
Tray
Tray
Tray
Version
PSC-4110
PSC-4110
PSC-4110
PSC-4110
PSC-4110
PSC-4110
PSC-4110
PSC-4110
PSC-4110
PSC-4110
PSC-4110
PSC-4110
Type number
DAC1653D; DAC1658D
© IDT 2014. All rights reserved.
Datasheet
Rev. 2.41 — 28 April 2014
3 of 168
DAC1653D/DAC1658D
Dual 16-bit DAC: 10 Gbps JESD204B interface: x2, x4 and x8 interpolating
Datasheet
5. B
LOCK DIAGRAM
DAC1653D; DAC1658D
Fig 1.
Block diagram
© IDT 2014. All rights reserved.
Datasheet
Rev. 2.41 — 28 April 2014
4 of 168
DAC1653D/DAC1658D
Dual 16-bit DAC: 10 Gbps JESD204B interface: x2, x4 and x8 interpolating
Datasheet
6. P
INNING INFORMATION
6.1 Pinning
Fig 2.
Pin configuration
6.2 Pin description
Table 2.
Symbol
AUXA_N
AUXA_P
CLKIN_P
CLKIN_N
SYSREF_W_P
SYSREF_W_N
V
DDD(1V2)
IO0
RF_ENABLE/IO1
V
DDD(1V2)
V
DDD(sync)
JRES
SYNC_OUT_N
DAC1653D; DAC1658D
Pin description
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
Type
[1]
Description
O
O
I
I
I/O
I/O
P
I/O
I/O
P
P
I/O
O
complementary auxiliary DAC A output current
auxiliary DAC A output current
DAC clock positive input
DAC clock negative input
multiple device synchronization positive signal, west side (if not used, keep it floating)
multiple device synchronization negative signal, west side (if not used, keep it floating)
1.2 V digital power supply
IO port bit 0
IO port bit 1 or RF enable pin (see Section automute)
1.2 V digital power supply
flexible power supply for SYNC differential signals (1.2 V to 1.8 V; see
Section 11.2.1.1)
calibration resistor (6.98 k 1%) for serial lanes termination
synchronization request to transmitter, complementary output
© IDT 2014. All rights reserved.
Datasheet
Rev. 2.41 — 28 April 2014
5 of 168
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