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74LVC1G58GW

Description
Low-power configurable multiple function gate
Categorylogic    logic   
File Size78KB,18 Pages
ManufacturerPhilips Semiconductors (NXP Semiconductors N.V.)
Websitehttps://www.nxp.com/
Download Datasheet Parametric Compare View All

74LVC1G58GW Overview

Low-power configurable multiple function gate

74LVC1G58GW Parametric

Parameter NameAttribute value
Is it Rohs certified?incompatible
MakerPhilips Semiconductors (NXP Semiconductors N.V.)
package instructionTSSOP, TSSOP6,.08
Reach Compliance Codeunknow
JESD-30 codeR-PDSO-G6
JESD-609 codee0
Load capacitance (CL)50 pF
MaximumI(ol)0.024 A
Number of terminals6
Maximum operating temperature125 °C
Minimum operating temperature-40 °C
Package body materialPLASTIC/EPOXY
encapsulated codeTSSOP
Encapsulate equivalent codeTSSOP6,.08
Package shapeRECTANGULAR
Package formSMALL OUTLINE, THIN PROFILE, SHRINK PITCH
method of packingTAPE AND REEL
power supply3.3 V
Prop。Delay @ Nom-Su7.9 ns
Certification statusNot Qualified
Schmitt triggerYES
Nominal supply voltage (Vsup)3.3 V
surface mountYES
technologyCMOS
Temperature levelAUTOMOTIVE
Terminal surfaceTin/Lead (Sn/Pb)
Terminal formGULL WING
Terminal pitch0.635 mm
Terminal locationDUAL
74LVC1G58
Low-power configurable multiple function gate
Rev. 01 — 15 September 2004
Product data sheet
1. General description
The 74LVC1G58 is a high-performance, low-power, low-voltage, Si-gate CMOS device,
superior to most advanced CMOS compatible TTL families.
Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of this
device in a mixed 3.3 V and 5 V environment.
This device is fully specified for partial power-down applications using I
off
. The I
off
circuitry
disables the output, preventing the damaging backflow current through the device when it
is powered down.
The 74LVC1G58 provides configurable multiple functions. The output state is determined
by eight patterns of 3-bit input. The user can choose the logic functions AND, OR, NAND,
NOR, XOR, inverter and buffer. All inputs can be connected to V
CC
or GND.
The three inputs (A, B and C) are capable of transforming slowly changing input signals
into sharply defined, jitter-free output signals.
The gate switches at different points for positive and negative-going signals. The
difference between the positive voltage V
T+
and the negative voltage V
T−
is defined as the
hysteresis voltage V
H
.
2. Features
s
s
s
s
Wide supply voltage range from 1.65 V to 5.5 V
5 V tolerant input/output for interfacing with 5 V logic
High noise immunity
Complies with JEDEC standard:
x
JESD8-7 (1.65 V to 1.95 V)
x
JESD8-5 (2.3 V to 2.7 V)
x
JESD8B/JESD36 (2.7 V to 3.6 V).
±24
mA output drive (V
CC
= 3.0 V)
ESD protection:
x
HBM EIA/JESD22-A114-B exceeds 2000 V
x
MM EIA/JESD22-A115-A exceeds 200 V.
CMOS low power consumption
Latch-up performance exceeds 250 mA
Direct interface with TTL levels
Inputs accept voltages up to 5 V
Multiple package options
Specified from
−40 °C
to +85
°C
and
−40 °C
to +125
°C.
s
s
s
s
s
s
s
s

74LVC1G58GW Related Products

74LVC1G58GW 74LVC1G58 74LVC1G58GM 74LVC1G58GV
Description Low-power configurable multiple function gate Low-power configurable multiple function gate Low-power configurable multiple function gate Low-power configurable multiple function gate
Is it Rohs certified? incompatible - incompatible incompatible
Maker Philips Semiconductors (NXP Semiconductors N.V.) - Philips Semiconductors (NXP Semiconductors N.V.) Philips Semiconductors (NXP Semiconductors N.V.)
package instruction TSSOP, TSSOP6,.08 - SON, SOLCC6,.04,20 TSOP, TSOP6,.11,37
Reach Compliance Code unknow - unknow unknow
JESD-30 code R-PDSO-G6 - R-PDSO-N6 R-PDSO-G6
JESD-609 code e0 - e0 e0
Load capacitance (CL) 50 pF - 50 pF 50 pF
MaximumI(ol) 0.024 A - 0.024 A 0.024 A
Number of terminals 6 - 6 6
Maximum operating temperature 125 °C - 125 °C 125 °C
Minimum operating temperature -40 °C - -40 °C -40 °C
Package body material PLASTIC/EPOXY - PLASTIC/EPOXY PLASTIC/EPOXY
encapsulated code TSSOP - SON TSOP
Encapsulate equivalent code TSSOP6,.08 - SOLCC6,.04,20 TSOP6,.11,37
Package shape RECTANGULAR - RECTANGULAR RECTANGULAR
Package form SMALL OUTLINE, THIN PROFILE, SHRINK PITCH - SMALL OUTLINE SMALL OUTLINE, THIN PROFILE
method of packing TAPE AND REEL - TAPE AND REEL TAPE AND REEL
power supply 3.3 V - 3.3 V 3.3 V
Prop。Delay @ Nom-Su 7.9 ns - 7.9 ns 7.9 ns
Certification status Not Qualified - Not Qualified Not Qualified
Schmitt trigger YES - YES YES
Nominal supply voltage (Vsup) 3.3 V - 3.3 V 3.3 V
surface mount YES - YES YES
technology CMOS - CMOS CMOS
Temperature level AUTOMOTIVE - AUTOMOTIVE AUTOMOTIVE
Terminal surface Tin/Lead (Sn/Pb) - Tin/Lead (Sn/Pb) Tin/Lead (Sn/Pb)
Terminal form GULL WING - NO LEAD GULL WING
Terminal pitch 0.635 mm - 0.5 mm 0.95 mm
Terminal location DUAL - DUAL DUAL
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