Supports 100 MHz and 125 MHz reference clock frequencies
–
Flexible port clocking modes
•
Common clock
•
Non-common clock
•
Local port clock with SSC (spread spectrum setting) and port
reference clock input
Hot-Plug and Hot Swap
–
Hot-plug controller on all ports
•
Hot-plug supported on all downstream switch ports
–
All ports support hot-plug using low-cost external I
2
C I/O
expanders
–
Configurable presence-detect supports card and cable appli-
cations
–
GPE output pin for hot-plug event notification
•
Enables SCI/SMI generation for legacy operating system
support
–
Hot-swap capable I/O
Power Management
–
Supports D0, D3hot and D3 power management states
–
Active State Power Management (ASPM)
•
Supports L0, L0s, L1, L2/L3 Ready, and L3 link states
•
Configurable L0s and L1 entry timers allow performance/
power-savings tuning
–
SerDes power savings
•
Supports low swing / half-swing SerDes operation
•
SerDes associated with unused ports are turned off
•
SerDes associated with unused lanes are placed in a low
power state
Reliability, Availability, and Serviceability (RAS)
–
ECRC support
–
AER on all ports
–
SECDED ECC protection on all internal RAMs
–
End-to-end data path parity protection
–
Checksum Serial EEPROM content protected
–
Ability to generate an interrupt (INTx or MSI) on link up/down
transitions
Initialization / Configuration
–
Supports Root (BIOS, OS, or driver), Serial EEPROM, or
SMBus switch initialization
–
Common switch configurations are supported with pin strap-
ping (no external components)
–
Supports in-system Serial EEPROM initialization/program-
ming
On-Die Temperature Sensor
–
Range of 0 to 127.5 degrees Celsius
–
Three programmable temperature thresholds with over and
under temperature threshold alarms
–
Automatic recording of maximum high or minimum low
temperature
9 General Purpose I/O
Test and Debug
–
Ability to inject AER errors simplifies in system error handling
software validation
–
On-chip link activity and status outputs available for several
ports
–
Per port link activity and status outputs available using
external I
2
C I/O expander for all remaining ports
–
Supports IEEE 1149.6 AC JTAG and IEEE 1149.1 JTAG
Standards and Compatibility
–
PCI Express Base Specification 2.1 compliant
–
Implements the following optional PCI Express features
•
Advanced Error Reporting (AER) on all ports
•
End-to-End CRC (ECRC)
•
Access Control Services (ACS)
•
Device Serial Number Enhanced Capability
•
Sub-System ID and Sub-System Vendor ID Capability
•
Internal Error Reporting
•
Multicast
•
VGA and ISA enable
•
L0s and L1 ASPM
•
ARI
Power Supplies
–
Requires three power supply voltages (1.0V, 2.5V, and 3.3V)
Packaged in a 23mm x 23mm 484-ball Flip Chip BGA with
1mm ball spacing
Product Description
With Non-Transparent Bridging functionality and innovative Switch
Partitioning feature, the PES32NT24BG2 allows true multi-host or multi-
processor communications in a single device. Integrated DMA control-
lers enable high-performance system design by off-loading data transfer
operations across memories from the processors. Each lane is capable
of 5 GT/s link speed in both directions and is fully compliant with PCI
Express Base Specification 2.1.
A non-transparent bridge (NTB) is required when two PCI Express
domains need to communicate to each other. The main function of the
NTB block is to initialize and translate addresses and device IDs to
allow data exchange across PCI Express domains. The major function-
alities of the NTB block are summarized in
Table 1.
2 of 37
December 17, 2013
IDT 89HPES32NT24BG2 Datasheet
Block Diagram
x8
x4
x2
x1
x1
x1
x2
x1
x1
x2
x1
x1
x4
x2
x1
S e rD e s
D L /T L
S e rD es
D L /T L
Se rD e s
D L/T L
S e rD e s
D L /T L
Se rD e s
D L/T L
S erD es
D L /T L
S e rD e s
D L/T L
S e rD e s
D L /T L
SerDes
SerDes
DL/TL
DL/TL
x2
x4
x2
NT B
NT B
NTB
N TB
DL/TL
SerDes
DL/TL
x4
x2
x8
SerDes
x2
x8
DM A
DL/TL
24-Po rt Sw itc h C o re
NT B
NT B
N TB
NTB
DM A
SerDes
DL/TL
x2
x4
SerDes
DL/TL
x2
x2
x4
x2
SerDes
SerDes
DL/TL
D L /T L
S e rD e s
D L /T L
Se rD e s
D L /T L
S e rD es
D L /T L
Se rD e s
D L /T L
S e rD es
D L /T L
Se rD e s
D L /T L
S erD es
D L /T L
S e rD e s
x1
x2
x1
x1
x2
x4
x1
x1
x2
x1
x1
x2
x4
x1
x8
Figure 1 PES32NT24BG2 Block Diagram
Function
NTB ports
Mapping table
entries
Mapping windows
Number
Up to 8
Up to 64 for entire
device
Six 32-bits or three
64-bits
Description
Each device can be configured to have up to 8 NTB functions and can support up to 8 CPUs/roots.
Each device can have up to 64 masters ID for address and ID translations.
Each NT port has six BARs, where each BAR opening an NT window to another domain.
Lookup-table translation divides the BAR aperture into up to 24 segments, where each segment
has independent translation programming and is associated with an entry in a look-up table.
Doorbell register is used for event signaling between domains, where an outbound doorbell bit sets
a corresponding bit at the inbound doorbell in the other domain.
Message registers allow mailbox message passing between domains -- message placed in the
inbound register will be seen at the outbound register at the other domain.
Table 1 Non-Transparent Bridge Function Summary
Address translation Direct-address and
lookup table trans-
lations
Doorbell registers
Message registers
32 bits
4 inbound and out-
bound registers of
32-bits
3 of 37
December 17, 2013
IDT 89HPES32NT24BG2 Datasheet
SMBus Interface
The PES32NT24BG2 contains two SMBus interfaces. The slave interface provides full access to the configuration registers in the
PES32NT24BG2, allowing every configuration register in the device to be read or written by an external agent. The master interface allows the default
configuration register values of the PES32NT24BG2 to be overridden following a reset with values programmed in an external serial EEPROM. The
master interface is also used by an external Hot-Plug I/O expander.
Each of the two SMBus interfaces contain an SMBus clock pin and an SMBus data pin. In addition, the slave SMBus has an SSMBADDR2 pin. As
shown in
Figure 2,
the master and slave SMBuses may only be used in a split configuration. In the split configuration, the master and slave SMBuses
operate as two independent buses; thus, multi-master arbitration is not required. The SMBus master interface does not support SMBus arbitration. As
a result, the switch’s SMBus master must be the only master in the SMBus lines that connect to the serial EEPROM and I/O expander slaves.
Switch
Processor
SMBus
Master
...
Other
SMBus
Devices
SSMBCLK
SSMBDAT
MSMBCLK
MSMBDAT
Serial
EEPROM
Hot-Plug
I/O
Expander
Figure 2 Split SMBus Interface Configuration
Hot-Plug Interface
The PES32NT24BG2 supports PCI Express Hot-Plug on each downstream port (ports 1 through 23). To reduce the number of pins required on the
device, the PES32NT24BG2 utilizes an external I/O expander, such as that used on PC motherboards, connected to the SMBus master interface.
Following reset and configuration, whenever the state of a Hot-Plug output needs to be modified, the PES32NT24BG2 generates an SMBus transac-
tion to the I/O expander with the new value of all of the outputs. Whenever a Hot-Plug input changes, the I/O expander generates an interrupt which is
received on the IOEXPINTN input pin (alternate function of GPIO) of the PES32NT24BG2. In response to an I/O expander interrupt, the
PES32NT24BG2 generates an SMBus transaction to read the state of all of the Hot-Plug inputs from the I/O expander.
General Purpose Input/Output
The PES32NT24BG2 provides 9 General Purpose I/O (GPIO) pins that may be individually configured as general purpose inputs, general purpose
outputs, or alternate functions. All GPIO pins are shared with other on-chip functions. These alternate functions may be enabled via software, SMBus
slave interface, or serial configuration EEPROM.
Pin Description
The following tables list the functions of the pins provided on the PES32NT24BG2. Some of the functions listed may be multiplexed onto the same
pin. The active polarity of a signal is defined using a suffix. Signals ending with an “N” are defined as being active, or asserted, when at a logic zero
(low) level. All other signals (including clocks, buses, and select lines) will be interpreted as being active, or asserted, when at a logic one (high) level.
Differential signals end with a suffix “N” or “P.” The differential signal ending in “P” is the positive portion of the differential pair and the differential signal
ending in “N” is the negative portion of the differential pair.
Note:
Pin [x] of a port refers to a lane. For port 0, PE00RN[0] refers to lane 0, PE00RN[1] refers to lane 1, etc.
This is a program I bought from Taobao, but I can't understand it myself, so please take up some of your time. The three pictures are the main program, and the other one is the schematic diagram....
The waveform has a dead zone. How to calculate the duty cycle of the output PWM waveform?I defined the dead zone in the program. The duty cycle without the dead zone is 34%, and the period is 50 micro...
I know that the communication between MFC program and driver is carried out through DeviceIoControl function, but if the driver wants to return some information to MFC program, how to achieve it? Plea...
I want to make the LCD display a screen similar to a PDA interface after the board is powered on, and I can select items by pressing buttons. How can I do this? Can uC/Gui do this?...
It is said that when PCB is wiring, the line width should be kept constant.If they are inconsistent, reflections may occur or the resistance value may be difficult to calculate.In a double-layer board...
In the process of using computers, it is inevitable to encounter many sudden failures. These failures may be caused by software reasons, hardware failures, or other factors... So, how should we, the p...
The TIA Portal software's shift instructions shift the contents of an accumulator bit by bit to the left or right. The number of bits shifted is determined by N. A left shift of N bits multiplies t...[Details]
To understand why car engines need gearboxes, we must first understand the characteristics of different types of engines. An engine refers to a machine that can convert a form of energy into kineti...[Details]
With the rapid development of technology, automotive intelligence is increasing at an unprecedented rate. This not only enhances vehicle functionality and comfort, but also places higher deman...[Details]
Current Development Status of DVR Market
A DVR, or digital video recorder, uses a hard disk for recording, unlike traditional analog video recorders. It's often called a DVR because it's a com...[Details]
On August 25th, Apple's expansion in India encountered new troubles. According to Bloomberg, Foxconn Technology Group has recalled approximately 300 Chinese engineers from India, further hindering ...[Details]
Common Mode Semiconductor has officially released its latest generation of power management ICs—the GM6506 series. This fully integrated high-frequency synchronous rectification step-down p...[Details]
introduction
The concept of the smart home is gradually developing and gaining market acceptance. We believe its ultimate form lies in the interconnection of all home appliances through open i...[Details]
With the rapid development of electric vehicles in my country, people are beginning to pay attention to the issue of radiation from electric vehicles. We all know that mobile phones emit radiation,...[Details]
Methods of DC motor speed regulation:
1. The voltage regulator can be used to change the input voltage and speed directly, which is often used for large kilowatt-level motors.
2. Thyristo...[Details]
Batteries, at the core of new energy vehicles, are crucial to vehicle performance and range. Existing automotive batteries are categorized into lead-acid and lithium batteries. Currently, new energ...[Details]
Civilian internal combustion engines operate in the range of approximately 1000-4000 rpm. This results in the engine's kinetic energy being ineffective at low or high rpm, making starting difficult...[Details]
New version helps developers build secure and trustworthy embedded systems
Shanghai, China—August 21, 2025—
QNX, a division of BlackBerry Ltd., today announced the release of QNX...[Details]
introduction
In today's busy society, people experience chronic high stress, which in turn poses a significant threat to our health. Therefore, effectively relieving stress has become a pr...[Details]
Hair dryer structure and working principle: It is mainly used for drying and shaping hair, but it can also be used for local drying, heating and treatment in laboratories, physiotherapy rooms, ind...[Details]
introduction
The rapid development of science and technology has enabled mankind to quickly move from the Internet era to the big data era. As a result, the amount of data generated by people ...[Details]
51mcu
京公网安备 11010802033920号
EEWORLD
