3D7005-100 datasheet, PDF - EEWORLD Datasheet

3D7005-100: DescriptionSilicon Delay Line, 1-Func, 5-Tap, True Output, CMOS, PDIP14, 0.300 INCH, DIP-14; Categorylogic logic; File Size158KB，4 Pages; ManufacturerData Delay Devices; Environmental Compliance

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3D7005-100 Overview

Silicon Delay Line, 1-Func, 5-Tap, True Output, CMOS, PDIP14, 0.300 INCH, DIP-14

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Parts packaging code	DIP
package instruction	DIP-14
Contacts	14
Reach Compliance Code	compliant
Other features	MAX FAN OUT OF 10 74LS LOAD PER OUTPUT; MAX RISE TIME CAPTURED
series	3D
Input frequency maximum value (fmax)	16 MHz
JESD-30 code	R-PDIP-T14
length	19.4 mm
Load capacitance (CL)	25 pF
Logic integrated circuit type	SILICON DELAY LINE
Number of functions	1
Number of taps/steps	5
Number of terminals	14
Maximum operating temperature	70 °C
Minimum operating temperature
Output polarity	TRUE
Package body material	PLASTIC/EPOXY
encapsulated code	DIP
Encapsulate equivalent code	DIP14,.3
Package shape	RECTANGULAR
Package form	IN-LINE
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
Maximum supply current (ICC)	5 mA
programmable delay line	NO
Certification status	Not Qualified
Maximum seat height	4.31 mm
Maximum supply voltage (Vsup)	5.25 V
Minimum supply voltage (Vsup)	4.75 V
Nominal supply voltage (Vsup)	5 V
surface mount	NO
technology	CMOS
Temperature level	COMMERCIAL
Terminal form	THROUGH-HOLE
Terminal pitch	2.54 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED
Total delay nominal (td)	100 ns
width	7.62 mm
Base Number Matches	1

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