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S1D13505F00A200

Description
CRT OR FLAT PNL GRPH DSPL CTLR, PQFP128, QFP15-128
CategoryThe embedded processor and controller    Microcontrollers and processors   
File Size109KB,2 Pages
ManufacturerSeiko Epson Corporation
Environmental Compliance
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S1D13505F00A200 Overview

CRT OR FLAT PNL GRPH DSPL CTLR, PQFP128, QFP15-128

S1D13505F00A200 Parametric

Parameter NameAttribute value
Is it lead-free?Lead free
Is it Rohs certified?conform to
MakerSeiko Epson Corporation
Parts packaging codeQFP
package instructionFQFP,
Contacts128
Reach Compliance Codecompliant
Is SamacsysN
Address bus width21
Bus compatibilityISA; PCMCIA; 68000; 68030; MPC821; E0C33
External data bus width16
JESD-30 codeS-PQFP-G128
JESD-609 codee6
length14 mm
Humidity sensitivity level3
Number of terminals128
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
Package body materialPLASTIC/EPOXY
encapsulated codeFQFP
Package shapeSQUARE
Package formFLATPACK, FINE PITCH
Peak Reflow Temperature (Celsius)260
Certification statusNot Qualified
Maximum supply voltage5.5 V
Minimum supply voltage2.7 V
Nominal supply voltage3 V
surface mountYES
technologyCMOS
Temperature levelINDUSTRIAL
Terminal surfaceTin/Bismuth (Sn/Bi)
Terminal formGULL WING
Terminal pitch0.4 mm
Terminal locationQUAD
Maximum time at peak reflow temperature10
width14 mm
uPs/uCs/peripheral integrated circuit typeDISPLAY CONTROLLER, CRT OR FLAT PANEL GRAPHICS DISPLAY
Base Number Matches1
GRAPHICS
S1D13505
S1D13505 Embedded RAMDAC LCD/CRT Controller
DESCRIPTION
The S1D13505 is a color/monochrome LCD/CRT graphics controller interfacing to a wide range of CPUs and display
devices. The S1D13505 architecture is designed to meet the low cost, low power requirements of the embedded
markets, such as Mobile Communications, Hand-Held PCs, and Office Automation.
The S1D13505 supports multiple CPUs, all LCD panel types, CRT, and additionally provides a number of
differentiating features. Products requiring a “Portrait” mode display can take advantage of the SwivelView feature.
Simultaneous, Virtual and Split Screen Display are just some of the display modes supported, while the Hardware
Cursor, Ink Layer, and the Memory Enhancement Registers offer substantial performance benefits. These features,
combined with the S1D13505’s Operating System independence, make it an ideal display solution for a wide variety
of applications.
February 2009
FEATURES
Memory Interface
16-bit EDO-DRAM or FPM-DRAM interface.
Memory size options:
512K bytes using one 256K×16 device.
2M bytes using one 1M×16 device.
Addressable as a single linear address space.
CPU Interface
Supports the following interfaces:
Hitachi SH-4.
Hitachi SH-3.
Motorola M68K.
Philips MIPS PR31500/PR31700.
Toshiba MIPS TX3912.
Motorola Power PC MPC821.
NEC MIPS VR4102/VR4111.
Epson E0C33.
PC Card (PCMCIA).
StrongARM (PC Card).
ISA bus.
MPU bus interface with programmable READY.
CPU write buffer.
Display Support
4/8-bit monochrome passive LCD interface.
4/8/16-bit color passive LCD interface.
Single-panel, single-drive displays.
Dual-panel, dual-drive displays.
Direct support for 9/12-bit TFT/D-TFD; 18-bit TFT/D-TFD
is supported up to 64K color depth (16-bit data).
Embedded RAMDAC with direct analog CRT drive.
Simultaneous display of CRT and passive or TFT/D-TFD
panels.
Display Modes
1/2/4/8/16 bit-per-pixel (bpp) support on LCD/CRT.
Up to 16 shades of gray using FRM on monochrome
passive LCD panels.
Up to 4096 colors on passive LCD panels.
Up to 64K colors on active matrix TFT/D-TFD LCD
panels and CRT in 16 bpp modes.
Split Screen Display: allows two different images to be
simultaneously viewed on the same display.
Virtual Display Support: displays images larger than the
display size through the use of panning.
Double Buffering/multi-pages: provides smooth
animation and instantaneous screen update.
SwivelView: direct hardware 90° rotation of
display image for portrait mode display.
Acceleration of screen updates by allocating full
display memory bandwidth to CPU.
Hardware 64x64 pixel 2-bit cursor or full screen
2-bit ink layer.
Clock Source
Single clock input for both pixel and memory clocks.
Memory clock can be input clock or (input clock/2),
providing flexibility to use CPU bus clock as input.
Pixel clock can be memory clock or (memory clock/2) or
(memory clock/3) or (memory clock/4).
Power Down Modes
Software power save mode.
LCD power sequencing.
General Purpose IO Pins
Up to 3 General Purpose IO pins are available.
Operating Voltage
Maximum resolution of 800x600 pixels at a color
depth of 16 bpp.
2.7 volts to 5.5 volts.
Package
128-pin QFP15 surface mount package.
X23A-C-002-15
Revision 15.2
1

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