ICS601M-01T datasheet, PDF - EEWORLD Datasheet

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ICS601M-01T: DescriptionClock Generator, 156MHz, CMOS, PDSO16, 0.150 INCH, SOIC-16; CategoryThe embedded processor and controller Microcontrollers and processors; File Size172KB，9 Pages; ManufacturerIDT (Integrated Device Technology)

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ICS601M-01T Overview

Clock Generator, 156MHz, CMOS, PDSO16, 0.150 INCH, SOIC-16

ICS601M-01T Parametric

Parameter Name	Attribute value
Is it lead-free?	Contains lead
Is it Rohs certified?	incompatible
Maker	IDT (Integrated Device Technology)
Parts packaging code	SOIC
package instruction	0.150 INCH, SOIC-16
Contacts	16
Reach Compliance Code	not_compliant
ECCN code	EAR99
Is Samacsys	N
JESD-30 code	R-PDSO-G16
JESD-609 code	e0
length	9.9 mm
Number of terminals	16
Maximum operating temperature	70 °C
Minimum operating temperature
Maximum output clock frequency	156 MHz
Package body material	PLASTIC/EPOXY
encapsulated code	SOP
Encapsulate equivalent code	SOP16,.25
Package shape	RECTANGULAR
Package form	SMALL OUTLINE
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
power supply	3.3/5 V
Master clock/crystal nominal frequency	27 MHz
Certification status	Not Qualified
Maximum seat height	1.75 mm
Maximum slew rate	30 mA
Maximum supply voltage	5.5 V
Minimum supply voltage	3 V
Nominal supply voltage	3.3 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	GULL WING
Terminal pitch	1.27 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED
width	3.9 mm
uPs/uCs/peripheral integrated circuit type	CLOCK GENERATOR, OTHER
Base Number Matches	1

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DATASHEET

LOW PHASE NOISE CLOCK MULTIPLIER

Description

The ICS601-01 is a low-cost, low phase noise,

high-performance clock synthesizer for applications

which require low phase noise and low jitter. It is IDT’s

lowest phase noise multiplier, and also the lowest

CMOS part in the industry. Using IDT’s patented

analog and digital Phase-Locked Loop (PLL)

techniques, the chip accepts a 10 - 27 MHz crystal or

clock input, and produces output clocks up to 156 MHz

at 3.3 V.

This product is intended for clock generation. It has low

output jitter (variation in the output period), but input to

output skew and jitter are not defined nor guaranteed.

For applications which require definted input to output

timing, use the ICS670-01.

ICS601-01

Features

•

Packaged in 16-pin SOIC or TSSOP

Available in Pb (lead) free package

Uses fundamental 10 - 27 MHz crystal or clock

Patented PLL with the lowest phase noise

Output clocks up to 156 MHz at 3.3 V

Low phase noise: -132 dBc/Hz at 10 kHz

Low jitter - 18 ps one sigma typ.

Full swing CMOS outputs with 25 mA drive capability

at TTL levels

•

Advanced, low power, sub-micron CMOS process

•

Industrial temperature range available

•

Operating voltage of 3.3V or 5V

NOTE: EOL for non-green parts to occur on

5/13/10 per PDN U-09-01

Block Diagram

VDD

Reference

Divider

Phase

Comparator

Charge

Pump

Loop

Filter

VCO

CLK

X1/ICLK

Crystal or

clock input

Crystal

Oscillator

ROM Based

Multipliers

REFOUT

VCO

Divide

S3:0

GND

REFEN

IDT™ / ICS™

LOW PHASE NOISE CLOCK MULTIPLIER

ICS601-01

REV M 102709

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