CY22393
CY22394
CY22395
Three-PLL Serial-Programmable
Flash-Programmable Clock Generator
Features
• Three integrated phase-locked loops (PLLs)
• Ultra wide divide counters (8-bit Q, 11-bit P, and 7-bit post
divide)
• Improved linear crystal load capacitors
• Flash programmability with external programmer
• Field-programmable
• Low jitter, high accuracy outputs
• Power management options (Shutdown, OE, Suspend)
• Configurable crystal drive strength
• Frequency select via three external LVTTL inputs
• 3.3V operation
• 16-pin TSSOP package
• CyClocksRT™ software support
Benefits
• Generates up to three unique frequencies on up to six
outputs from an external source.
• Allows for 0 ppm frequency generation and frequency
conversion in the most demanding applications.
• Improves frequency accuracy over temperature, age,
process, and initial ppm offset.
• Nonvolatile programming enables easy customization,
ultra-fast turnaround, performance tweaking, design timing
margin testing, inventory control, lower part count, and more
secure product supply. In addition, any part in the family can
be programmed multiple times, which reduces
programming errors and provides an easy upgrade path for
existing designs.
• In-house programming of samples and prototype quantities
is available using the CY3672 FTG Development Kit.
Production quantities are available through Cypress
Semiconductor’s value-added distribution partners or by
using third-party programmers from BP Microsystems, HiLo
Systems, and others.
• Performance suitable for high-end multimedia, communica-
tions, industrial, A/D converters, and consumer applica-
tions.
• Supports numerous low power application schemes and
reduces electromagnetic interference (EMI) by allowing
unused outputs to be turned off.
• Adjust crystal drive strength for compatibility with virtually
all crystals.
• 3-bit external frequency select options for PLL1, CLKA, and
CLKB.
• Industry standard packaging saves on board space.
• Easy to use software support for design entry.
• I
2
C interface allows in-system programming into volatile
configuration memory. All frequency settings can be
changed, providing literally millions of frequency options.
• Adjust output buffer strength to lower EMI or improve timing
margin.
• Fine tune crystal oscillator frequency by changing load
capacitance.
• Differential output up to 400 MHz.
• Provides interfacing option for low voltage parts.
Advanced Features
•
•
•
•
•
I
2
C serial interface for in-system configurability
Configurable output buffer
Digital VCXO
High frequency LVPECL output (CY22394 only)
3.3/2.5V outputs (CY22395 only)
Cypress Semiconductor Corporation
Document #: 38-07186 Rev. *C
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised March 13, 2007
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CY22393
CY22394
CY22395
Selector Guide
Part Number
CY22393FC
CY22393FI
CY22394FC
CY22394FI
CY22395FC
CY22395FI
Outputs
6 CMOS
6 CMOS
1 PECL/
4 CMOS
1 PECL/
4 CMOS
Input Frequency Range
Output Frequency Range
Specifics
Commercial Temperature
Industrial Temperature
Commercial Temperature
Industrial Temperature
Commercial Temperature
Industrial Temperature
8 MHz–30 MHz (external crystal) Up to 200 MHz
1 MHz–166 MHz (reference clock)
8 MHz–30 MHz (external crystal) Up to 166 MHz
1 MHz–150 MHz (reference clock)
8 MHz–30 MHz (external crystal) 100 MHz–400 MHz (PECL)
1 MHz–166 MHz (reference clock) Up to 200 MHz (CMOS)
8 MHz–30 MHz (external crystal) 125 MHz–375 MHz (PECL)
1 MHz–150 MHz (reference clock) Up to 166 MHz (CMOS)
4 LVCMOS/ 8 MHz–30 MHz (external crystal) Up to 200 MHz (3.3V)
1 CMOS
1 MHz–166 MHz (reference clock) Up to 133 MHz (2.5V)
4 LVCMOS/ 8 MHz–30 MHz (external crystal) Up to 166 MHz (3.3V)
1 CMOS
1 MHz–150 MHz (reference clock) Up to 133 MHz (2.5V)
Logic Block Diagram — CY22393
XTALIN
XTALOUT
OSC.
XBUF
CONFIGURATION
FLASH
PLL1
11-Bit P
8-Bit Q
PLL2
11-Bit P
8-Bit Q
PLL3
11-Bit P
8-Bit Q
Divider
7-Bit
CLKB
4x4
Crosspoint
Switch
Divider
/2, /3, or /4
CLKE
SHUTDOWN/OE
SCLK
SDAT
S2/SUSPEND
Divider
7-Bit
CLKD
Divider
7-Bit
CLKC
Divider
7-Bit
CLKA
Logic Block Diagram — CY22394
XTALIN
XTALOUT
OSC.
XBUF
CONFIGURATION
FLASH
PLL1
11-Bit P
8-Bit Q
0º
180º
PECL
OUTPUT
P+CLK
P-CLK
SHUTDOWN/OE
SCLK
SDAT
S2/SUSPEND
PLL2
11-Bit P
8-Bit Q
4x4
Crosspoint
Switch
Divider
7-Bit
CLKC
PLL3
11-Bit P
8-Bit Q
Divider
7-Bit
CLKB
Divider
7-Bit
CLKA
Document #: 38-07186 Rev. *C
Page 2 of 17
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CY22393
CY22394
CY22395
Logic Block Diagram — CY22395
XTALIN
XTALOUT
OSC.
Divider
/2, /3, or /4
PLL1
11-Bit P
8-Bit Q
SHUTDOWN/OE
SCLK
SDAT
S2/SUSPEND
PLL2
11-Bit P
8-Bit Q
Divider
7-Bit
LCLKB
4x4
Crosspoint
Switch
Divider
7-Bit
Divider
7-Bit
LCLKD
LCLKE
CONFIGURATION
FLASH
CLKC
PLL3
11-Bit P
8-Bit Q
Divider
7-Bit
LCLKA
LCLKA, LCLKB, LCLKD, LCLKE referenced to LVDD
Pin Configurations
CY22393
16-pin TSSOP
CLKC
V
DD
AGND
XTALIN
XTALOUT
XBUF
CLKD
CLKE
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
SHUTDOWN/OE
S2/SUSPEND
AV
DD
SCLK (S1)
SDAT (S0)
GND
CLKA
CLKB
CLKC
V
DD
AGND
XTALIN
XTALOUT
XBUF
P–CLK
P+ CLK
CY22394
16-pin TSSOP
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
SHUTDOWN/OE
S2/SUSPEND
AV
DD
SCLK (S1)
SDAT (S0)
GND
CLKA
CLKB
CLKC
V
DD
AGND
XTALIN
XTALOUT
LV
DD
LCLKD
LCLKE
CY22395
16-pin TSSOP
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
SHUTDOWN/OE
S2/SUSPEND
AV
DD
SCLK (S1)
SDAT (S0)
GND/LGND
LCLKA
LCLKB
Pin Definitions
Name
CLKC
V
DD
AGND
XTALIN
XTALOUT
XBUF
LV
DD
CLKD or LCLKD
P– CLK
CLKE or LCLKE
P+ CLK
Pin Number Pin Number Pin Number
CY22393
CY22394
CY22395
1
2
3
4
5
6
N/A
7
N/A
8
N/A
1
2
3
4
5
6
N/A
N/A
7
N/A
8
1
2
3
4
5
N/A
6
7
N/A
8
N/A
Power supply
Analog Ground
Reference crystal input or external reference clock input
Reference crystal feedback
Buffered reference clock output
Low voltage clock output power supply
Configurable clock output D; LCLKD referenced to LVDD
LV PECL output
[1]
Configurable clock output E; LCLKE referenced to LVDD
LV PECL output
[1]
Description
Configurable clock output C
Note
1. LVPECL outputs require an external termination network.
Document #: 38-07186 Rev. *C
Page 3 of 17
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CY22393
CY22394
CY22395
Pin Definitions
(continued)
Name
CLKB or LCLKB
CLKA or LCLKA
GND/LGND
SDAT (S0)
SCLK (S1)
AV
DD
S2/
SUSPEND
SHUTDOWN/
OE
Pin Number Pin Number Pin Number
CY22393
CY22394
CY22395
9
10
11
12
13
14
15
16
9
10
11
12
13
14
15
16
9
10
11
12
13
14
15
16
Description
Configurable clock output B; LCLKB referenced to LVDD
Configurable clock output A; LCLKA referenced to LVDD
Ground
Serial Port (I
2
C) Data. S0 value latched during start up
Serial Port (I
2
C) Clock. S1 value latched during start up
Analog Power Supply
General purpose input for frequency control; bit 2. Optionally,
Suspend mode control input
Places outputs in tri-state condition and shuts down chip when
LOW. Optionally, only places outputs in tri-state condition and
does not shut down chip when LOW
The two frequency settings are contained within an eight-row
frequency table. The values of SCLK (S1) and SDAT (S0) pins
are latched during start up and used as the other two indexes
into this array.
CLKA and CLKB have seven-bit dividers that point to one of
the two programmable settings (register 0 and register 1). Both
clocks share a single register control and both must be set to
register 0, or both must be set to register 1.
For example, the part may be programmed to use S0, S1, and
S2 (0,0,0 to 1,1,1) to control eight different values of P and Q
on PLL1. For each PLL1 P and Q setting, one of the two CLKA
and CLKB divider registers can be chosen. Any divider change
as a result of switching S0, S1, or S2 is guaranteed to be glitch
free.
Crystal Input
The input crystal oscillator is an important feature of this family
of parts because of its flexibility and performance features.
The oscillator inverter has programmable drive strength. This
allows for maximum compatibility with crystals from various
manufacturers, process, performance, and quality.
The input load capacitors are placed on-die to reduce external
component cost. These capacitors are true parallel-plate
capacitors for ultra-linear performance. These were chosen to
reduce the frequency shift that occurs when nonlinear load
capacitance interacts with load, bias, supply, and temperature
changes. Nonlinear (FET gate) crystal load capacitors should
not be used for MPEG, POTS dial tone, communications, or
other applications that are sensitive to absolute frequency
requirements.
The value of the load capacitors is determined by six bits in a
programmable register. The load capacitance can be set with
a resolution of 0.375 pF for a total crystal load range of 6 pF
to 30 pF.
For driven clock inputs, the input load capacitors can be
completely bypassed. This allows the clock chip to accept
driven frequency inputs up to 166 MHz. If the application
requires a driven input, leave XTALOUT floating.
Operation
The CY22393, CY22394, and CY22395 are a family of parts
designed as upgrades to the existing CY22392 device. These
parts have similar performance to the CY22392, but provide
advanced features to meet the needs of more demanding
applications.
The clock family has three PLLs which, when combined with
the reference, allow up to four independent frequencies to be
output on up to six pins. These three PLLs are completely
programmable.
Configurable PLLs
PLL1 generates a frequency that is equal to the reference
divided by an 8-bit divider (Q) and multiplied by an 11-bit
divider in the PLL feedback loop (P). The output of PLL1 is sent
to two locations: the cross point switch and the PECL output
(CY22394). The output of PLL1 is also sent to a /2, /3, or /4
synchronous post-divider that is output through CLKE. The
frequency of PLL1 can be changed using serial programming
or by external CMOS inputs, S0, S1, and S2. See the following
section on
General Purpose Inputs
for more detail.
PLL2 generates a frequency that is equal to the reference
divided by an 8-bit divider (Q) and multiplied by an 11-bit
divider in the PLL feedback loop (P). The output of PLL2 is sent
to the cross point switch. The frequency of PLL2 is changed
using serial programming.
PLL3 generates a frequency that is equal to the reference
divided by an 8-bit divider (Q) and multiplied by an 11-bit
divider in the PLL feedback loop (P). The output of PLL3 is sent
to the cross point switch. The frequency of PLL3 is changed
using serial programming.
General Purpose Inputs
S2 is a general purpose input that is programmed to allow for
two different frequency settings. Options that switches with
this general purpose input are as follows: the frequency of
PLL1, the output divider of CLKB, and the output divider of
CLKA.
Document #: 38-07186 Rev. *C
Page 4 of 17
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CY22393
CY22394
CY22395
Digital VCXO
The serial programming interface is used to dynamically
change the capacitor load value on the crystal. A change in
crystal load capacitance corresponds with a change in the
reference frequency.
For special pullable crystals specified by Cypress, the capac-
itance pull range is +150 ppm to –150 ppm from midrange.
Be aware that adjusting the frequency of the reference affects
all frequencies on all PLLs in a similar manner since all
frequencies are derived from the single reference.
Output Configuration
Under normal operation there are four internal frequency
sources that are routed via a programmable cross point switch
to any of the four programmable 7-bit output dividers. The four
sources are: reference, PLL1, PLL2, and PLL3. The following
is a description of each output.
CLKA’s output originates from the cross point switch and goes
through a programmable 7-bit post divider. The 7-bit post
divider derives its value from one of the two programmable
registers.
See the section on “General Purpose Inputs” on
page 4
for more information.
CLKB’s output originates from the cross point switch and goes
through a programmable 7-bit post divider. The 7-bit post
divider derives its value from one of the two programmable
registers.
See the section on “General Purpose Inputs” on
page 4
for more information.
CLKC’s output originates from the cross point switch and goes
through a programmable 7-bit post divider. The 7-bit post
divider derives its value from one programmable register.
CLKD’s output originates from the cross point switch and goes
through a programmable 7-bit post divider. The 7-bit post
divider derives its value from one programmable register. For
the CY22394, CLKD is brought out as the complimentary
version of a LV PECL Clock referenced to CLKE, bypassing
both the cross point switch and 7-bit post divider.
CLKE’s output originates from PLL1 and goes through a post
divider that may be programmed to /2, /3, or /4. For the
CY22394, CLKE is brought out as a low voltage PECL Clock,
bypassing the post divider.
XBUF is the buffered reference.
The Clock outputs have been designed to drive a single point
load with a total lumped load capacitance of 15 pF. While
driving multiple loads is possible with the proper termination it
is generally not recommended.
Power-Saving Features
The SHUTDOWN/OE input tri-states the outputs when pulled
LOW. If system shutdown is enabled, a LOW on this pin also
shuts off the PLLs, counters, reference oscillator, and all other
active components. The resulting current on the V
DD
pins is
less than 5 mA (typical). Relock the PLLs after leaving
shutdown mode.
The S2/SUSPEND input is configured to shut down a custom-
izable set of outputs and/or PLLs, when LOW. All PLLs and
any of the outputs are shut off in nearly any combination. The
only limitation is that if a PLL is shut off, all outputs derived from
it must also be shut off. Suspending a PLL shuts off all
Document #: 38-07186 Rev. *C
associated logic, while suspending an output simply forces a
tri-state condition.
With the serial interface, each PLL and/or output is individually
disabled. This provides total control over the power savings.
Improving Jitter
Jitter Optimization Control is useful for mitigating problems
related to similar clocks switching at the same moment,
causing excess jitter. If one PLL is driving more than one
output, the negative phase of the PLL can be selected for one
of the outputs (CLKA–CLKD). This prevents the output edges
from aligning, allowing superior jitter performance.
Power Supply Sequencing
For parts with multiple V
DD
pins, there are no power supply
sequencing requirements. The part is not fully operational until
all V
DD
pins have been brought up to the voltages specified in
the
Operating Conditions[2] Table on page 12.
All grounds should be connected to the same ground plane.
CyClocksRT Software
CyClocksRT is our second generation software application
that allows users to configure this family of devices. The
easy-to-use interface offers complete control of the many
features of this family including, but not limited to, input
frequency, PLL and output frequencies, and different
functional options. It checks data sheet frequency range limita-
tions and automatically applies performance tuning.
CyClocksRT also has a power estimation feature that allows
the user to see the power consumption of a specific configu-
ration. You can download a free copy of CyberClocks that
includes CyClocksRT for free on Cypress’s web site at
www.cypress.com.
CyClocksRT is used to generate P, Q, and divider values used
in serial programming. There are many internal frequency
rules that are not documented in this data sheet, but are
required for proper operation of the device. Check these rules
by using the latest version of CyClocksRT.
Junction Temperature Limitations
It is possible to program this family such that the maximum
Junction Temperature rating is exceeded. The package
θ
JA
is
115 °C/W. Use the CyClocksRT power estimation feature to
verify that the programmed configuration meets the Junction
Temperature and Package Power Dissipation maximum
ratings.
Dynamic Updates
The output divider registers are not synchronized with the
output clocks. Changing the divider value of an active output
will likely cause a glitch on that output.
PLL P and Q data is spread between three bytes. Each byte
becomes active on the acknowledge for that byte, so changing
P and Q data for an active PLL will likely cause the PLL to try
to lock on an out-of-bounds condition. For this reason, turn off
the PLL being programmed during the update. Do this by
setting the PLL*_En bit LOW.
PLL1, CLKA, and CLKB each have multiple registers
supplying data. To program these resources safely, always
Page 5 of 17
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