DS1350Y/AB
PRELIMINARY
DS1350Y/AB
4096K Nonvolatile SRAM
with Battery Monitor
FEATURES
PIN ASSIGNMENT
BW
A15
A16
RST
V
CC
WE
OE
CE
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
A18
A17
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
•
Built–in lithium battery provides more than 10 years of
data retention
•
Data
loss
is automatically protected during V
CC
power
•
Power
supply monitor resets processor when V
CC
power loss occurs and holds processor in reset during
V
CC
ramp–up
•
Battery monitor checks remaining capacity daily
•
Read and write access times as fast as 70 ns
•
Unlimited write cycle endurance
•
Typical standby current 50
µA
•
Upgrade
devices
for 512K x 8 SRAM, EEPROM or Flash
34–PIN LOW PROFILE MODULE (LPM)
•
Lithium battery is electrically disconnected to retain
freshness until power is applied for the first time
PIN DESCRIPTION
A0–A18
DQ0–DQ7
CE
WE
OE
RST
BW
V
CC
GND
NC
–
–
–
–
–
–
–
–
–
–
Address Inputs
Data In/Data Out
Chip Enable
Write Enable
Output Enable
Reset Output
Battery Warning Output
+5 Volts
Ground
No Connect
•
Full
±10%
V
CC
operating range (DS1350Y) or
optional
±5%
V
CC
operating range (DS1350AB)
surface mountable PLCC sockets
•
Low Profile Module package fits into standard 68–pin
•
Optional
industrial temperature range of –40°C to
+85°C, designated IND
DESCRIPTION
The DS1350 4096K Nonvolatile SRAMs are
4,194,304–bit, fully static, nonvolatile SRAMs orga-
nized as 524,288 words by eight bits. Each NV SRAM
has a self–contained lithium energy source and control
circuitry which constantly monitors V
CC
for an out–of–
tolerance condition. When such a condition occurs, the
lithium energy source is automatically switched on and
write protection is unconditionally enabled to prevent
data corruption. Additionally, the DS1350 devices have
dedicated circuitry for monitoring the status of V
CC
and
the status of the internal lithium battery. There is no limit
on the number of write cycles which can be executed,
and no additional support circuitry is required for micro-
processor interfacing. The devices can be used in place
of 512K x 8 SRAM, EEPROM or Flash components.
Available in the Low Profile Module package, DS1350
devices are specifically designed for surface mount
applications.
ECopyright
1995 by Dallas Semiconductor Corporation.
All Rights Reserved. For important information regarding
patents and other intellectual property rights, please refer to
Dallas Semiconductor data books.
041996 1/9
DS1350Y/AB
READ MODE
The DS1350 devices execute a read cycle whenever
WE (Write Enable) is inactive (high) and CE (Chip
Enable) and OE (Output Enable) are active (low). The
unique address specified by the 19 address inputs (A
0
-
A
18
) defines which of the 524,288 bytes of data is to be
accessed. Valid data will be available to the eight data
output drivers within t
ACC
(Access Time) after the last
address input signal is stable, providing that CE and OE
(Output Enable) access times are also satisfied. If OE
and CE access times are not satisfied, then data access
must be measured from the later occurring signal (CE or
OE) and the limiting parameter is either t
CO
for CE or t
OE
for OE rather than address access.
During power–up, when V
CC
rises above approximately
2.7 volts, the power switching circuit connects external
V
CC
to the RAM and disconnects the lithium energy
source. Normal RAM operation can resume after V
CC
exceeds 4.75 volts for the DS1350AB and 4.5 volts for
the DS1350Y.
SYSTEM POWER MONITORING
DS1350 devices have the ability to monitor the external
V
CC
power supply. When an out–of–tolerance power
supply condition is detected, the NV SRAMs warn a pro-
cessor–based system of impending power failure by
asserting RST. On power up, RST is held active for 200
ms nominal to prevent system operation during pow-
er–on transients and to allow t
REC
to elapse. RST has
an open–drain output driver.
WRITE MODE
The DS1350 devices excute a write cycle whenever the
WE and CE signals are in the active (low) state after
address inputs are stable. The later occurring falling
edge of CE or WE will determine the start of the write
cycle. The write cycle is terminated by the earlier rising
edge of CE or WE. All address inputs must be kept valid
throughout the write cycle. WE must return to the high
state for a minimum recovery time (t
WR
) before another
cycle can be initiated. The OE control signal should be
kept inactive (high) during write cycles to avoid bus con-
tention. However, if the output drivers are enabled (CE
and OE active) then WE will disable the outputs in t
ODW
from its falling edge.
BATTERY MONITORING
The DS1350 devices automatically perform periodic
battery voltage monitoring on a 24 hour time interval.
Such monitoring begins within t
REC
after V
CC
rises
above V
TP
and is suspended when power failure
occurs.
After each 24 hour period has elapsed, the battery is
connected to an internal 1MΩ test resistor for one
second. During this one second, if battery voltage falls
below the battery voltage trip point (2.6V), the battery
warning output BW is asserted. Once asserted, BW
remains active until the module is replaced. The battery
is still retested after each V
CC
power–up, however, even
if BW is active. If the battery voltage is found to be higher
than 2.6V during such testing, BW is de–asserted and
regular 24–hour testing resumes. BW has an open–
drain output driver.
DATA RETENTION MODE
The DS1350AB provides full functional capability for
V
CC
greater than 4.75 volts and write protects by 4.5
volts. The DS1350Y provides full functional capability
for V
CC
greater than 4.5 volts and write protects by 4.25
volts. Data is maintained in the absence of V
CC
without
any additional support circuitry. The nonvolatile static
RAMs constantly monitor V
CC
. Should the supply volt-
age decay, the NV SRAMs automatically write protect
themselves, all inputs become “don’t care,” and all out-
puts become high impedance. As V
CC
falls below
approximately 2.7 volts, the power switching circuit con-
nects the lithium energy source to RAM to retain data.
FRESHNESS SEAL AND SHIPPING
Each DS1350 is shipped from Dallas Semiconductor
with its lithium energy source disconnected, guarantee-
ing full energy capacity. When V
CC
is first applied at a
level greater than V
TP
, the lithium energy source is
enabled for battery backup operation.
041996 2/9
京公网安备 11010802033920号
EEWORLD
