FemtoClock
®
NG Crystal-to-HCSL
Clock Generator
G
ENERAL
D
ESCRIPTION
The 841604 is an optimized PCIe and sRIO clock generator.
The device uses a 25MHz parallel crystal to generate 100MHz
and 125MHz clock signals, replacing solutions requiring multiple
oscillator and fanout buffer solutions. The device has excellent phase
jitter (< 1ps rms) suitable to clock components requiring precise and
low-jitter PCIe or sRIO or both clock signals. Designed for telecom,
networking and industrial applications, the 841604 can also drive the
high-speed sRIO and PCIe SerDes clock inputs of communication
processors, DSPs, switches and bridges.
841604
DATASHEET
F
EATURES
• Four differential clock outputs: configurable for PCIe (100MHz)
and sRIO (125MHz) clock signals
• Selectable crystal oscillator interface, 25MHz, 18pF parallel
resonant crystal or LVCMOS/LVTTL single-ended reference
clock input
• Supports the following output frequencies:
100MHz or 125MHz
• VCO: 500MHz
• PLL bypass and output enable
• PCI Express (2.5Gb/s) and Gen 2 (5 Gb/s) jitter compliant
• RMS phase jitter, 125MHz, using a 25MHz crystal
(1.875MHz – 20MHz): 0.45ps (typical)
• Full 3.3V power supply mode
• -40°C to 85°C ambient operating temperature
• Available in lead-free (RoHS 6) package
B
LOCK
D
IAGRAM
XTAL_IN
P
IN
A
SSIGNMENT
1
Q0
nQ0
0
÷N
÷4
÷5
(default)
Q1
nQ1
OSC
XTAL_OUT
REF_IN
Pulldown
0
FemtoClock
PLL
1
VCO = 500MHz
REF_SEL
REF_IN
V
DD
GND
XTAL_IN
XTAL_OUT
MR/nOE
V
DD
nc
nc
nc
nc
GND
V
DD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
REF_SEL
Pulldown
Q2
M = ÷20
IREF
BYPASS
Pulldown
FSEL
Pulldown
MR/nOE
Pulldown
nQ2
Q3
nQ3
28
27
26
25
24
23
22
21
20
19
18
17
16
15
V
DDA
BYPASS
IREF
FSEL
V
DD
nQ3
Q3
nQ2
Q2
GND
nQ1
Q1
nQ0
Q0
841604
28-Lead TSSOP
6.1mm x 9.7mm x 0.925mm
package body
G Package
Top View
841604 REVISION A 4/17/15
1
©2015 Integrated Device Technology, Inc.
841604 DATA SHEET
T
ABLE
1. P
IN
D
ESCRIPTIONS
Number
1
2
3, 8, 14,
24
4, 13, 19
5, 6
Name
REF_SEL
REF_IN
V
DD
GND
XTAL_IN,
XTAL_OUT
MR/nOE
Input
Input
Power
Power
Input
Type
Pulldown
Description
Reference select. Selects the input reference source.
LVCMOS/LVTTL interface levels. See Table 3D.
Pulldown LVCMOS/LVTTL PLL reference clock input.
Core supply pins.
Power supply ground.
Parallel resonant crystal interface. XTAL_OUT is the output,
XTAL_IN is the input.
Active HIGH master reset. Active LOW output enable. When logic HIGH, the
internal dividers are reset and the outputs are in high impedance (Hi-Z). When
Pulldown
logic LOW, the internal dividers and the outputs are enabled. Asynchronous
function. LVCMOS/LVTTL interface levels. See Table 3C.
No connect.
Differential output pair. HCSL interface levels.
Differential output pair. HCSL interface levels.
Differential output pair. HCSL interface levels.
Differential output pair. HCSL interface levels.
Pulldown Output frequency select pin. LVCMOS/LVTTL interface levels. See Table 3A.
HCSL current reference resistor output. An external fixed precision resistor
(475W) from this pin to ground provides a reference current used for differen-
tial current-mode Qx/nQx clock outputs.
Selects PLL operation/PLL bypass operation. Asynchronous function. LLVC-
Pulldown
MOS/LVTTL interface levels. See Table 3B.
Analog supply pin.
7
9, 10, 11,
12
15, 16
17, 18
20, 21
22, 23
25
26
27
28
Input
nc
Q0, nQ0
Q1, nQ1
Q2, nQ2
Q3, nQ3
FSEL
IREF
BYPASS
V
DDA
Unused
Output
Output
Output
Output
Input
Output
Input
Power
NOTE:
Pulldown
refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
T
ABLE
2. P
IN
C
HARACTERISTICS
Symbol
C
IN
R
PULLDOWN
Parameter
Input Capacitance
Input Pulldown Resistor
= 25MH
Z
)
Test Conditions
Minimum
Typical
4
51
Maximum
Units
pF
kΩ
T
ABLE
3A. FSEL F
UNCTION
T
ABLE
(f
Input
FSEL
0
1
N
5
4
ref
T
ABLE
3B. BYPASS F
UNCTION
T
ABLE
Input
BYPASS
0
1
PLL Configuration
PLL enabled (default)
PLL bypassed (f
OUT
= f
REF
÷ N)
Outputs
Q0:1/nQ0:1
VCO/5 (100MHz) PCIe (default)
VCO/4 (125MHz) sRIO
T
ABLE
3C. MR/nOE F
UNCTION
T
ABLE
Input
MR/nOE
0
1
Function
Outputs enabled (default)
Device reset, outputs disabled (high-impedance)
T
ABLE
3D. REF_SEL F
UNCTION
T
ABLE
Input
REF_SEL
0
1
Input Reference
XTAL (default)
REF_IN
FEMTOCLOCKS™ CRYSTAL-TO-HCSL
CLOCK GENERATOR
2
REVISION A 4/17/15
841604 DATA SHEET
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
DD
Inputs, V
I
Outputs, V
O
Package Thermal Impedance,
θ
JA
Storage Temperature, T
STG
4.6V
-0.5V to V
DD
+ 0.5V
-0.5V to V
DD
+ 0.5V
64.5°C/W (0 mps)
-65°C to 150°C
N OT E : S t r e s s e s b eyo n d t h o s e l i s t e d u n d e r A b s o l u t e
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions beyond
those listed in the
DC Characteristics
or
AC Characteristics
is not
implied. Exposure to absolute maximum rating conditions for ex-
tended periods may affect product reliability.
T
ABLE
4A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= 3.3V±5%, T
A
= -40°C
TO
85°C
Symbol
V
DD
V
DDA
I
DD
I
DDA
Parameter
Core Supply Voltage
Analog Supply Voltage
Power Supply Current
Analog Supply Current
Test Conditions
Minimum
3.135
V
DD
– 0.15
Typical
3.3
3.3
Maximum
3.465
V
DD
87
15
Units
V
V
mA
mA
T
ABLE
4B. LVCMOS / LVTTL DC C
HARACTERISTICS
,
V
DD
= 3.3V±5%, T
A
= -40°C
TO
85°C
Symbol
V
IH
V
IL
I
IH
I
IL
Parameter
Input High Voltage
Input Low Voltage
Input
High Current
Input
Low Current
REF_IN, REF_SEL,
BYPASS, MR/nOE, FSEL
REF_IN, REF_SEL,
BYPASS, MR/nOE, FSEL
VDD = VIN = 3.465V
Test Conditions
Minimum
2
-0.3
Typical
Maximum
V + 0.3
DD
Units
V
V
µA
µA
0.8
150
VDD = 3.465V, VIN = 0V
-5
T
ABLE
5. C
RYSTAL
C
HARACTERISTICS
Parameter
Mode of Oscillation
Frequency
Equivalent Series Resistance (ESR)
Shunt Capacitance
NOTE: Characterized using an 18pF parallel resonant crystal.
Test Conditions
Minimum
Typical
25
50
7
Maximum
Units
MHz
Ω
pF
Fundamental
REVISION A 4/17/15
3
FEMTOCLOCKS™ CRYSTAL-TO-HCSL
CLOCK GENERATOR
841604 DATA SHEET
T
ABLE
6. AC C
HARACTERISTICS
,
V
DD
= 3.3V±5%, T
A
= -40°C
TO
85°C
Symbol
f
MAX
tjit(Ø)
Parameter
Output Frequency
RMS Phase Jitter (Random); NOTE 1
Test Conditions
VCO/5
VCO/4
100MHz, (1.875MHz - 20MHz)
125MHz, (1.875MHz - 20MHz)
100MHz, (1.2MHz – 50MHz),
10
6
samples, 25MHz crystal input
125MHz, (1.2MHz – 62.5MHz),
10
6
samples, 25MHz crystal input
100MHz, 10
6
samples,
25MHz crystal input
125MHz, 10
6
samples,
25MHz crystal input
Minimum Typical Maximum Units
100
125
0.36
0.45
12.81
12.30
1.32
1.19
50
75
0.6
0.6
-100
4
4
100
1150
-300
250
550
140
48
500
90
52
MHz
MHz
ps
ps
ps
ps
ps rms
ps rms
ps
ps
V/ns
V/ns
mV
mV
mV
mV
mV
%
ps
ms
T
j
Phase Jitter Peak-to-Peak; NOTE 2
T
REFCLK_HF_RMS
tjit(cc)
tsk(o)
Rise Edge
Rate
V
RB
V
MAX
V
MIN
V
CROSS
DV
CROSS
odc
T
STABLE
t
L
Phase Jitter RMS; NOTE 3
Cycle-to-Cycle Jitter; NOTE 4
Output Skew; NOTE 4, 5
Rising Edge Rate; NOTE 6, 7
Fall Edge Rate Falling Edge Rate; NOTE 6, 7
Ringback Voltage; NOTE 6, 8
Absolute Max. Output Voltage; NOTE
9, 10
Absolute Min. Output Voltage; NOTE
9, 11
Absolute Crossing Voltage;
NOTE 9, 12, 13
Total Variation of V
Cross
over all edges;
NOTE 9, 12, 14
Output Duty Cycle; NOTE 6, 15
Power-up Stable Clock Output; NOTE
6, 8
PLL Lock Time
NOTE: All specifi cations are taken at 100MHz and 125MHz.
NOTE 1: Please refer to the Phase Noise Plot.
NOTE 2: RMS jitter after applying system transfer function. See IDT Application Note, PCI Express Reference Clock Requirements. Maximum
limit for PCI Express is 86ps peak-to-peak.
NOTE 3: RMS jitter after applying system transfer function. The pole frequencies for H1 and H2 for PCIe Gen 2 are 8-16MHz and 5-16MHz.
See IDT Application Note, PCI Express Reference Clock Requirements.Maximum limit for PCI Express Generation 2 is 3.1ps rms.
NOTE 4: This parameter is defi ned in accordance with JEDEC Standard 65.
NOTE 5: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the output differential cross points.
NOTE 6: Measurement taken from differential waveform.
NOTE 7: Measurement from -150mV to +150mV on the differential waveform (derived from Qx minus nQx).
The signal must be monotonic through the measurement region for rise and fall time. The 300mV measurement window is centered on the
differential zero crossing. See Parameter Measurement Information Section.
NOTE 8: T
STABLE
is the time the differential clock must maintain a minimum ±150mV differential voltage after rising/falling edges before it is
allowed to drop back into the V
RB
±100 differential range. See Parameter Measurement Information Section.
NOTE 9: Measurement taken from single ended waveform.
NOTE 10: Defi ned as the maximum instantaneous voltage including overshoot. See Parameter Measurement Information Section.
NOTE 11: Defi ned as the minimum instantaneous voltage including undershoot. See Parameter Measurement Information Section.
NOTE 12: Measured at crossing point where the instantaneous voltage value of the rising edge of Qx equals the falling edge of nQx.
See Parameter Measurement Information Section.
NOTE 13: Refers to the total variation from the lowest crossing point to the highest, regardless of which edge is crossing.
Refers to all crossing points for this measurement. See Parameter Measurement Information Section.
NOTE 14: Defined as the total variation of all crossing voltage of rising Qx and falling nQx. This is the maximum allowed variance in the V
CROSS
for any particular system. See Parameter Measurement Information Section.
NOTE 15: Input duty cycle must be 50%.
FEMTOCLOCKS™ CRYSTAL-TO-HCSL
CLOCK GENERATOR
4
REVISION A 4/17/15
841604 DATA SHEET
T
YPICAL
P
HASE
N
OISE AT
100MH
Z
100MHz
RMS Phase Jitter (Random)
1.875MHz to 20MHz = 0.36ps (typical)
➤
PCIe Filter
Phase Noise Result by adding
a PCIe Filter to raw data
N
OISE
P
OWER
dBc
Hz
Raw Phase Noise Data
O
FFSET
F
REQUENCY
(H
Z
)
T
YPICAL
P
HASE
N
OISE AT
125MH
Z
125MHz
RMS Phase Jitter (Random)
1.875MHz to 20MHz = 0.45ps (typical)
➤
➤
PCIe Filter
Raw Phase Noise Data
➤
N
OISE
P
OWER
dBc
Hz
➤
Phase Noise Result by adding
a PCIe Filter to raw data
O
FFSET
F
REQUENCY
(H
Z
)
REVISION A 4/17/15
5
➤
FEMTOCLOCKS™ CRYSTAL-TO-HCSL
CLOCK GENERATOR
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