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RD48F4444PPVTQ0

Description
8M X 16 FLASH 1.8V PROM, 85 ns, PDSO56
Categorystorage    storage   
File Size1MB,102 Pages
ManufacturerIntel
Websitehttp://www.intel.com/
Download Datasheet Parametric View All

RD48F4444PPVTQ0 Overview

8M X 16 FLASH 1.8V PROM, 85 ns, PDSO56

RD48F4444PPVTQ0 Parametric

Parameter NameAttribute value
Is it Rohs certified?incompatible
MakerIntel
Parts packaging codeBGA
package instruction11 X 11 MM, 1.40 MM HEIGHT, SCSP-88/80
Contacts88/80
Reach Compliance Codecompliant
ECCN code3A991.B.1.A
Maximum access time88 ns
Other featuresSYNCHRONOUS BURST MODE OPERATION ALSO POSSIBLE
startup blockTOP
JESD-30 codeS-PBGA-B80
JESD-609 codee0
length11 mm
memory density1073741824 bit
Memory IC TypeFLASH
memory width16
Number of functions1
Number of terminals80
word count67108864 words
character code64000000
Operating modeASYNCHRONOUS
Maximum operating temperature85 °C
Minimum operating temperature-30 °C
organize64MX16
Package body materialPLASTIC/EPOXY
encapsulated codeLFBGA
Package shapeSQUARE
Package formGRID ARRAY, LOW PROFILE, FINE PITCH
Parallel/SerialPARALLEL
Peak Reflow Temperature (Celsius)240
Programming voltage1.8 V
Certification statusNot Qualified
Maximum seat height1.4 mm
Maximum supply voltage (Vsup)2 V
Minimum supply voltage (Vsup)1.7 V
Nominal supply voltage (Vsup)1.8 V
surface mountYES
technologyCMOS
Temperature levelOTHER
Terminal surfaceTIN LEAD
Terminal formBALL
Terminal pitch0.8 mm
Terminal locationBOTTOM
Maximum time at peak reflow temperature30
typeNOR TYPE
width11 mm
Intel StrataFlash
®
Embedded Memory
(P30)
1-Gbit P30 Family
Datasheet
Product Features
Security
— 85/88 ns initial access
— One-Time Programmable Registers:
• 64 unique factory device identifier bits
— 40 MHz with zero wait states, 20 ns clock-to-
• 64 user-programmable OTP bits
data output synchronous-burst read mode
• Additional 2048 user-programmable OTP bits
— 25 ns asynchronous-page read mode
— Selectable OTP Space in Main Array:
— 4-, 8-, 16-, and continuous-word burst mode
• 4x32KB parameter blocks + 3x128KB main
— Buffered Enhanced Factory Programming
blocks (top or bottom configuration)
(BEFP) at 5 µs/byte (Typ)
— Absolute write protection: V
PP
= V
SS
— 1.8 V buffered programming at 7 µs/byte (Typ)
— Power-transition erase/program lockout
Architecture
— Individual zero-latency block locking
— Multi-Level Cell Technology: Highest Density
— Individual block lock-down
at Lowest Cost
Software
— Asymmetrically-blocked architecture
— 20 µs (Typ) program suspend
— Four 32-KByte parameter blocks: top or
— 20 µs (Typ) erase suspend
bottom configuration
— Intel
®
Flash Data Integrator optimized
— 128-KByte main blocks
— Basic Command Set and Extended Command
Voltage and Power
Set compatible
— V
CC
(core) voltage: 1.7 V – 2.0 V
— Common Flash Interface capable
— V
CCQ
(I/O) voltage: 1.7 V – 3.6 V
Density and Packaging
— Standby current: 55 µA (Typ) for 256-Mbit
— 64/128/256-Mbit densities in 56-Lead TSOP
— 4-Word synchronous read current:
package
13 mA (Typ) at 40 MHz
— 64/128/256/512-Mbit densities in 64-Ball
Quality and Reliability
Intel
®
Easy BGA package
— Operating temperature: –40 °C to +85 °C
• 1-Gbit in SCSP is –30 °C to +85 °C
— 64/128/256/512-Mbit and 1-Gbit densities in
Intel
®
QUAD+ SCSP
— Minimum 100,000 erase cycles per block
— 16-bit wide data bus
— ETOX™ VIII process technology (130 nm)
High performance
The Intel StrataFlash
®
Embedded Memory (P30) product is the latest generation of Intel
StrataFlash
®
memory devices. Offered in 64-Mbit up through 1-Gbit densities, the P30 device
brings reliable, two-bit-per-cell storage technology to the embedded flash market segment.
Benefits include more density in less space, high-speed interface, lowest cost-per-bit NOR
device, and support for code and data storage. Features include high-performance synchronous-
burst read mode, fast asynchronous access times, low power, flexible security options, and three
industry standard package choices.
The P30 product family is manufactured using Intel
®
130 nm ETOX™ VIII process technology.
Order Number: 306666, Revision: 001
April 2005

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