PRELIMINARY DATA SHEET
MICRONAS
BSP 3505D
Baseband
Sound Processor
Edition Oct. 21, 1998
6251-481-1PD
MICRONAS
BSP 3505D
Contents
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Section
1.
1.1.
1.2.
1.3.
2.
2.1.
2.1.1.
2.2.
2.3.
2.4.
3.
3.1.
3.2.
3.2.1.
3.2.2.
3.2.3.
3.2.4.
3.3.
4.
4.1.
4.2.
4.3.
4.4.
4.4.1.
4.4.2.
4.4.3.
4.4.4.
4.4.5.
4.4.6.
4.4.7.
4.4.8.
4.4.9.
4.4.10.
4.4.11.
4.4.12.
4.4.13.
4.4.14.
4.5.
4.5.1.
4.5.2.
4.5.3.
4.5.4.
4.5.5.
Title
Introduction
BSP 3505D Integrated Functions
Features of the DSP-Section
Features of the Analog Section
Architecture of the BSP 3505D
Analog Section and SCART Switching Facilities
Standby Mode
BSP 3505DAudio Baseband Processing
Clock and Crystal Specifications
Digital Control Output Pins
I
2
C Bus Interface: Device and Subaddresses
Protocol Description
Proposal for BSP 3505D I
2
C Telegrams
Symbols
Write Telegrams
Read Telegrams
Examples
Start Up Sequence: Power Up and I
2
C-Controlling
Programming the BSP 3505D
Register ‘MODE_REG’
DSP Write Registers: Table and Addresses
DSP Read Registers: Table and Addresses
DSP Write Registers: Functions and Values
Volume Loudspeaker Channel
Balance Loudspeaker Channel
Bass Loudspeaker Channel
Treble Loudspeaker Channel
Loudness Loudspeaker Channel
Spatial Effects Loudspeaker Channel
Volume SCART1
Channel Source Modes
Channel Matrix Modes
SCART Prescale
Definition of Digital Control Output Pins
Definition of SCART-Switching Facilities
Beeper
Automatic Volume Correction (AVC)
DSP Read Registers: Functions and Values
Quasi-Peak Detector
BSP Hardware Version Code
BSP Major Revision Code
BSP Product Code
BSP ROM Version Code
PRELIMINARY DATA SHEET
2
Micronas
PRELIMINARY DATA SHEET
BSP 3505D
Contents, continued
Page
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Section
5.
5.1.
5.2.
5.3.
5.4.
5.5.
5.5.1.
5.5.2.
5.5.3.
6.
7.
8.
Title
Specifications
Outline Dimensions
Pin Connections and Short Descriptions
Pin Configurations
Pin Circuits
Electrical Characteristics
Absolute Maximum Ratings
Recommended Operating Conditions
Characteristics
Application Circuit
Appendix A: BSP 3505D Version History
Data Sheet History
Micronas
3
BSP 3505D
Baseband Sound Processor
Release Notes: The hardware description in this
document is valid for the BSP 3505D version A2.
1. Introduction
The
BSP 3505D
is designed as a single-chip Baseband
Sound Processor for applications in analog and digital
TV sets, video recorders, and satellite receivers.
The IC is produced in submicron CMOS technology, and
is fully pin and software compatible to the MSP 34xx
family. The BSP 3505D is available in a PLCC68,
PSDIP64, PSDIP52, PQFP80, and in a PQFP44 pack-
age.
Note:
The BSP 3505D version has reduced control reg-
isters and less functional pins. The remaining registers
are software compatible to the MSP 34xxD. The pinning
is compatible to the MSP 34xxD.
1.1. BSP 3505D Integrated Functions
– Stereo baseband input via integrated A/D converters
– Two stereo D/A converters
– AVC: Automatic Volume Correction
– Bass, treble, volume, loudness processing
– Full SCART in/out matrix without restrictions
– spatial effect (pseudostereo / basewidth enlargement)
– Digital control output pins D_CTR_OUT0/1
– Reduction of necessary controlling
– Less external components
MONO IN
2
2
PRELIMINARY DATA SHEET
1.2. Features of the DSP-Section
– flexible selection of audio sources to be processed
– digital baseband processing: volume, bass, treble,
loudness, and spatial effects
– simple controlling of volume, bass, treble, loudness,
and spatial effects
1.3. Features of the Analog Section
– two selectable analog stereo audio baseband inputs
(= two SCART inputs)
input level:
≤2
V RMS,
input impedance:
≥25
kΩ
– one selectable analog mono input:
input level:
≤2
V RMS,
input impedance:
≥15
kΩ
– stereo high-quality A/D converter, S/N-Ratio:
≥85
dB
– 20 Hz to 20 kHz bandwidth for SCART-to-SCART-
copy facilities
– loudspeaker: stereo four-fold oversampled D/A-con-
verter
output level per channel: max. 1.4 VRMS
output resistance: max. 5 kΩ
S/N-ratio:
≥85
dB at maximum volume
max. noise voltage in mute mode:
≤10 µV
(BW: 20 Hz ...16 kHz)
– stereo four-fold oversampled D/A converter supplying
a stereo SCART-output
output level per channel: max. 2 V RMS,
output resistance: max. 0.5 kΩ,
S/N-Ratio:
≥85
dB (20 Hz...16 kHz)
2 I
2
C
2
Loudspeaker
OUT
SCART1 IN
SCART2 IN
BSP 3505D
2
SCART
OUT
Fig. 1–2:
Main I/O Signals BSP 3505D
Tuner
SIF
VIF
FM/AM Mono
Loudspeaker
SCART1
SCART
Inputs
SCART2
2
BSP 3505D
2
SCART1
SCART
Output
2
Fig. 1–1:
Typical BSP 3505D application
4
Micronas
PRELIMINARY DATA SHEET
BSP 3505D
SCART_IN
SC1_IN_L/R
2. Architecture of the BSP 3505D
Fig. 2–2 shows a simplified block diagram of the IC. Its
architecture is split into two main functional blocks:
1. DSP (digital signal processing) section performing
audio baseband processing
2. analog section containing two A/D-converters,
four D/A-converters, and SCART-switching facilities.
2.1. Analog Section and SCART Switching Facilities
The analog input and output sections include full matrix
switching facilities, which are shown in Fig. 2–1.
The switches are controlled by the ACB bits defined in
the audio processing interface (see section 4. Program-
ming the BSP 3505D).
2.1.1. Standby Mode
If the BSP 3505D is switched off by first pulling STAND-
BYQ low, and then disconnecting the 5 V, but keeping
the 8 V power supply (‘Standby’-mode), the switches
S1 and S2 (see Fig. 2–1) maintain their position and
function. This facilitates the copying from selected
SCART-inputs to SCART-output in the TV-set’s standby
mode.
In case of power-on start or starting from standby, the IC
switches automatically to the default configuration,
shown in Fig. 2–1. This action takes place after the first
I
2
C transmission into the DSP part. By transmitting the
ACB register first, the individual default setting mode of
the TV set can be defined.
SC2_IN_L/R
to Audio Baseband
Processing (DSP_IN)
A
D
SCARTL/R
MONO_IN
S1
intern. Sig-
nal Lines
Pins
SCART_OUT
from Audio Baseband
Processing (DSP_OUT)
SCART1_L/R
D
A
SC1_OUT_L/R
S2
Fig. 2–1:
SCART-Switching Facilities (see 4.4.12.)
positions show the default configuration after Power
On Reset.
Note:
SCART_OUT is undefined after RESET!
XTAL_IN
XTAL_OUT
Clock
DSP
LOUD-
SPEAKER L
LOUD-
SPEAKER R
D_CTR_OUT0/1
D/A
D/A
DACM_L
Loudspeaker
DACM_R
Mono
MONO_IN
SC1_IN_L
A/D
A/D
SCARTL
SCARTR
SCART1_L
SCART1_R
D/A
D/A
SC1_OUT_L
SCART1
SC1_IN_R
SCART
SC1_OUT_R
SC2_IN_L
SCART2
SC2_IN_R
SCART Switching Facilities
Fig. 2–2:
Architecture of the BSP 3505D
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5
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