PIC18(L)F24/25/45K50
PIC18(L)F24/25/45K50 Family
Silicon Errata and Data Sheet Clarification
The PIC18(L)F24/25/45K50 family devices that you
have received conform functionally to the current
Device Data Sheet (DS30684A), except for the
anomalies described in this document.
The silicon issues discussed in the following pages are
for silicon revisions with the Device and Revision IDs
listed in
Table 1.
The silicon issues are summarized in
Table 2.
The errata described in this document will be addressed
in future revisions of the PIC18(L)F24/25/45K50 silicon.
Note:
This document summarizes all silicon
errata issues from all revisions of silicon,
previous as well as current. Only the
issues indicated in the last column of
Table 2
apply to the current silicon
revision (A2).
For example, to identify the silicon revision level
using MPLAB IDE in conjunction with a hardware
debugger:
1.
2.
3.
4.
Using the appropriate interface, connect the
device to the hardware debugger.
Open an MPLAB IDE project.
Configure the MPLAB IDE project for the
appropriate device and hardware debugger.
Based on the version of MPLAB IDE you are
using, do one of the following:
a) For MPLAB IDE 8, select
Programmer >
Reconnect.
b) For MPLAB X IDE, select
Window >
Dashboard
and click the
Refresh Debug
Tool Status
icon (
).
Depending on the development tool used, the
part number
and
Device Revision ID value
appear in the
Output
window.
Note:
If you are unable to extract the silicon
revision level, please contact your local
Microchip sales office for assistance.
5.
Data Sheet clarifications and corrections start on
page
5,
following the discussion of silicon issues.
The silicon revision level can be identified using the
current version of MPLAB
®
IDE and Microchip’s
programmers, debuggers, and emulation tools, which
are available at the Microchip corporate web site
(www.microchip.com).
The DEVREV values for the various PIC18(L)F24/25/
45K50 silicon revisions are shown in
Table 1.
TABLE 1:
SILICON DEVREV VALUES
Device
ID
(1)
5C6h
5CEh
5C2h
5CAh
5C0h
5C8h
(11-bit)
Revision ID for Silicon Revision
(2)
(5-bit)
A1
0 0001
0 0001
0 0001
0 0001
0 0001
0 0001
A2
0 0010
0 0010
0 0010
0 0010
0 0010
0 0010
Part Number
PIC18F24K50
PIC18LF24K50
PIC18F25K50
PIC18LF25K50
PIC18F45K50
PIC18LF45K50
Note 1:
2:
The Device IDs (DEVID and DEVREV) are located at the last two implemented addresses of configuration
memory space. They are shown in hexadecimal in the format “DEVID:DEVREV”.
Refer to the
“PIC18(L)F2X/4XK50 Flash Memory Programming Specification”
(DS41630) for detailed
information on Device and Revision IDs for your specific device.
2012-2014 Microchip Technology Inc.
DS80000547C-page 1
PIC18(L)F24/25/45K50
TABLE 2:
Module
Oscillator
SILICON ISSUE SUMMARY
Feature
Fail-Safe Clock Monitor
Item
Number
1.
Issue Summary
HS oscillator remains biased if the crystal fails
and the clock has switched to Fail-Safe Clock,
causing high Sleep currents.
When using the Timer1 or Timer3 module as an
Asynchronous Counter either separately or
simultaneously, a false overflow interrupt can
occur after reloading the TMRxL and TMRxH
registers.
Affected
Revisions
(1)
A1
X
A2
X
Timer1/3
Asynchronous Counter
Module with
Mode
Gate Control
2.
X
X
Note 1:
Only those issues indicated in the last column apply to the current silicon revision.
DS80000547C-page 2
2012-2014 Microchip Technology Inc.
PIC18(L)F24/25/45K50
Silicon Errata Issues
Note:
This document summarizes all silicon
errata issues from all revisions of silicon,
previous as well as current. Only the
issues indicated by the shaded column in
the following tables apply to the current
silicon revision (A2).
1. Module: Oscillator
Higher Sleep currents will be observed if the HS
oscillator fails and the PIC
®
MCU switches to the
Fail-Safe Clock.
Issue occurs if:
- The device is running off of the HS clock
- The device experiences a failure on the
HS clock and the Fail-Safe Clock
activates
- The device then goes to Sleep without
the HS clock returning
- The Sleep current observed will differ
from base I
PD
by an amount equal to the
HS bias current.
Work around
None.
Affected Silicon Revisions
A1
X
A2
X
2012-2014 Microchip Technology Inc.
DS80000547C-page 3
PIC18(L)F24/25/45K50
2. Module: Timer1/3 Module with Gate
Control
When using the Timer1 or Timer3 module, either
separately or simultaneously, a false overflow
event may occur after reloading the timer. The
event only occurs when the timer is configured for
Asynchronous Counter mode operation, and is
only problematic if the timer's interrupt is enabled.
During the Interrupt Service Routine (ISR), after
reloading the timer register (TMR1 and/or TMR3)
with a new value, the false overflow event can
occur upon the very next increment of the timer.
This sets the TMRx Overflow Interrupt Flag bit
(TMRxIF) and if the timer’s interrupts are enabled,
the interrupt service handler will again branch to
the interrupt vector on the next instruction clock,
after leaving the ISR. If interrupts are not enabled,
the TMRx Overflow Interrupt Flag bit will be set,
however, the firmware will not branch to the
interrupt vector.
Work around
While inside the Interrupt Service Routine (ISR),
create a loop routine that tests the timer for a
minimum increment of one count. Once the timer
has incremented by a minimum of one count, test
the Overflow Interrupt Flag bit (TMRxIF) and clear
it if set before leaving the ISR.
EXAMPLE 1:
Load TMRx
movlw
movlwf
movlw
movwf
movf
CheckTMR
cpfsgt
goto
btfsc
bcf
btfss
bsf
TMR1/3 FALSE INTERRUPT WORK AROUND
0xAA
TMR3H
0x55
TMR3L
TMRxL, W
TMRxL, 0
CheckTMR
PIRx, TMRxIF
PIRx, TMRxIF
INTCON,
INTCON,
GIE
GIE
;W = 0xAA
;Load TMRxH with W
;W = 0x55
;Load TMRxL with W
;Move TMRxL to W
;Compare f with W, skip if f>W
;Goto CheckTMR if TMRx has not incremented yet
;Test for false TMRxIF
;Clear TMRx Overflow Interrupt Flag bit
;Test if
disabled
all
interrupts
including
including
peripherals
peripherals
were
if
;Enable
all
interrupts
disabled retfie
Affected Silicon Revisions
A1
X
A2
X
DS80000547C-page 4
2012-2014 Microchip Technology Inc.
PIC18(L)F24/25/45K50
Data Sheet Clarifications
The following typographic corrections and clarifications
are to be noted for the latest version of the device data
sheet (DS30684A):
Note:
Corrections are shown in
bold.
Where
possible, the original bold text formatting
has been removed for clarity.
1. Module: CPU Divider
Figure 3-1
from
Section 3.1 “Overview”,
as
well as
Table 3-6
and
Table 3-7
from
Section
3.14.1 “Low-Speed Operation”
have incorrect
data on the CPUDIV Configuration bits. The
corrected versions are below:
2012-2014 Microchip Technology Inc.
DS80000547C-page 5
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