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935219470518

Description
ALVT SERIES, 18-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO56, 7.50 MM, PLASTIC, MO-118, SOT-371-1, SSOP-56
Categorylogic    logic   
File Size118KB,20 Pages
ManufacturerNXP
Websitehttps://www.nxp.com
Download Datasheet Parametric View All

935219470518 Overview

ALVT SERIES, 18-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO56, 7.50 MM, PLASTIC, MO-118, SOT-371-1, SSOP-56

935219470518 Parametric

Parameter NameAttribute value
Objectid8074804377
package instructionSSOP,
Reach Compliance Codeunknown
Other featuresCAN ALSO OPERATE AT 3.3V SUPPLY
seriesALVT
JESD-30 codeR-PDSO-G56
JESD-609 codee4
length18.425 mm
Logic integrated circuit typeREGISTERED BUS TRANSCEIVER
Number of digits18
Number of functions1
Number of ports2
Number of terminals56
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
Output characteristics3-STATE
Output polarityTRUE
Package body materialPLASTIC/EPOXY
encapsulated codeSSOP
Package shapeRECTANGULAR
Package formSMALL OUTLINE, SHRINK PITCH
propagation delay (tpd)5.2 ns
Maximum seat height2.8 mm
Maximum supply voltage (Vsup)2.7 V
Minimum supply voltage (Vsup)2.3 V
Nominal supply voltage (Vsup)2.5 V
surface mountYES
technologyBICMOS
Temperature levelINDUSTRIAL
Terminal surfaceNICKEL PALLADIUM GOLD
Terminal formGULL WING
Terminal pitch0.635 mm
Terminal locationDUAL
width7.5 mm
74ALVT16601
18-bit universal bus transceiver; 3-state
Rev. 03 — 5 July 2005
Product data sheet
1. General description
The 74ALVT16601 is a high-performance Bipolar Complementary Metal Oxide
Semiconductor (BiCMOS) product designed for V
CC
operation at 2.5 V and 3.3 V with I/O
compatibility up to 5 V. This device is an 18-bit universal transceiver featuring
non-inverting 3-state bus compatible outputs in both send and receive directions. Data
flow in each direction is controlled by output enable (OEAB and OEBA), latch enable
(LEAB and LEBA), and clock (CPAB and CPBA) inputs. For A-to-B data flow, the device
operates in the transparent mode when LEAB is HIGH. When LEAB is LOW, the A-bus
data is latched if CPAB is held at a HIGH or LOW level. If LEAB is LOW, the A-bus data is
stored in the latch/flip-flop on the LOW-to-HIGH transition of CPAB. When OEAB is LOW,
the outputs are active. When OEAB is HIGH, the outputs are in the high-impedance state.
The clocks can be controlled with the clock enable inputs (CEAB and CEBA).
Data flow for B-to-A is similar to that of A-to-B but uses OEBA, LEBA and CPBA.
Active bus hold circuitry is provided to hold unused or floating data inputs at a valid logic
level.
2. Features
s
s
s
s
s
s
s
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s
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18-bit bidirectional bus interface
5 V I/O compatible
3-state buffers
Output capability: +64 mA and
−32
mA
TTL input and output switching levels
Input and output interface capability to systems at 5 V supply
Bus hold data inputs eliminate the need for external pull-up resistors to hold unused
inputs
Live insertion and extraction permitted
Power-up reset
Power-up 3-state
No bus current loading when output is tied to 5 V bus
Positive-edge triggered clock inputs
Latch-up protection:
x
JESD78: exceeds 500 mA
ESD protection:
x
MIL STD 883, method 3015: exceeds 2000 V
x
Machine model: exceeds 200 V
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