FW32306T100-DB datasheet, PDF - EEWORLD Datasheet

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FW32306T100-DB: DescriptionSerial I/O Controller, 3 Channel(s), 50MBps, CMOS, PQFP100, TQFP-100; CategoryThe embedded processor and controller Microcontrollers and processors; File Size334KB，18 Pages; ManufacturerLSC/CSI; Websitehttps://lsicsi.com

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FW32306T100-DB Overview

Serial I/O Controller, 3 Channel(s), 50MBps, CMOS, PQFP100, TQFP-100

FW32306T100-DB Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	LSC/CSI
Parts packaging code	QFP
package instruction	TQFP-100
Contacts	100
Reach Compliance Code	compliant
Address bus width	32
boundary scan	NO
Bus compatibility	PCI
maximum clock frequency	24.5785 MHz
Maximum data transfer rate	50 MBps
External data bus width	32
JESD-30 code	S-PQFP-G100
JESD-609 code	e0
length	14 mm
low power mode	YES
Number of serial I/Os	3
Number of terminals	100
Maximum operating temperature	70 °C
Minimum operating temperature
Package body material	PLASTIC/EPOXY
encapsulated code	LFQFP
Encapsulate equivalent code	QFP100,.63SQ,20
Package shape	SQUARE
Package form	FLATPACK, LOW PROFILE, FINE PITCH
Peak Reflow Temperature (Celsius)	240
power supply	3.3 V
Certification status	Not Qualified
Maximum seat height	1.6 mm
Maximum supply voltage	3.6 V
Minimum supply voltage	3 V
Nominal supply voltage	3.3 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	TIN LEAD
Terminal form	GULL WING
Terminal pitch	0.5 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	30
width	14 mm
uPs/uCs/peripheral integrated circuit type	SERIAL IO/COMMUNICATION CONTROLLER, SERIAL
Base Number Matches	1

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Product Brief

September 2004

™

FW323 06 T100

1394A

PCI PHY/Link Open Host Controller Interf

ace

Features

1394a-2000

OHCI link and PHY core function in a

single device:

— 100-pin TQFP package (also available in a lead-

free package*).

— Single-chip link and PHY enable smaller, simpler,

more efficient motherboard and add-in card

designs.

— Enables lower system costs.

— Leverages proven

1394a-2000

PHY core design.

— Demonstrated compatibility with current

Microsoft

Windows

drivers and common applications.

—

Demonstrated interoperability with existing, as well

as older,

1394

™

consumer electronics and periph-

erals products.

— Feature-rich implementation for high performance

in common applications.

— Supports low-power system designs (CMOS

implementation, power management features).

OHCI:

— Complies with the

1394 OHCI 1.1 Specification.

— OHCI 1.0 backwards compatible—configurable via

PCI bus commands to operate in either OHCI 1.0

or OHCI 1.1 mode.

— Complies with

Microsoft Windows

logo program

system and device requirements.

— Listed on

Windows

hardware compatibility list

http://www.microsoft.com/hcl/results.asp.

— Compatible with

Microsoft Windows

and

MacOS

operating systems.

— 4 Kbyte isochronous transmit FIFO.

— 2 Kbyte asynchronous transmit FIFO.

— 4 Kbyte isochronous receive FIFO.

— 2 Kbyte asynchronous receive FIFO.

— Dedicated asynchronous and isochronous

descriptor-based DMA engines.

— Eight isochronous transmit contexts.

— Eight isochronous receive contexts.

— Prefetches isochronous transmit data.

— Supports posted write transactions.

— Supports parallel processing of incoming physical

read and write requests.

— Supports notification (via interrupt) of a failed

1394a-2000

PHY core:

— Compliant with

IEEE

1394a-2000, Standard for a

High Performance Serial Bus

(Supplement).

* In an effort to better serve its customers and the environment,

Agere is switching to lead-free packaging on this product (no

intentional addition of lead).

— Provides three fully compliant cable ports, each

supporting 400 Mbits/s, 200 Mbits/s, and

100 Mbits/s traffic.

— Supports extended BIAS_HANDSHAKE time for

enhanced interoperability with camcorders.

— While unpowered and connected to the bus, will

not drive TPBIAS on a connected port even if

receiving incoming bias voltage on that port.

— Does not require external filter capacitor for PLL.

— Supports link-on as a part of the internal

PHY core-link interface.

— 25 MHz crystal oscillator and internal PLL provide

50 MHz

internal

link-layer controller clock as

well as

transmit/receive data at 100 Mbits/s,

200 Mbits/s, and 400 Mbits/s.

— Interoperable across

1394

cable with

1394

phys-

ical layers (PHY core) using 5 V supplies.

— Provides node power-class information signaling

for system power management.

— Supports ack-accelerated arbitration and fly-by

concatenation.

— Supports arbitrated short bus reset to improve

utilization of the bus.

— Fully supports suspend/resume.

— Supports connection debounce.

— Supports multispeed packet concatenation.

— Supports PHY pinging and remote PHY access

packets.

— Provides separate cable bias and driver termina-

tion voltage supply for each port.

Link:

— Cycle master and isochronous resource manager

capable.

— Supports

1394a-2000

acceleration features.

PCI:

— Revision 2.2 compliant.

— 33 MHz/32-bit operation.

— Programmable burst size thresholds for PCI data

transfer.

— Supports optimized memory read line, memory

read multiple, and memory write invalidate burst

commands.

— Supports

PCI Bus Power Management Interface

Specification

v.1.1.

— Global byte-swap function.

Note:

This device does not support D3cold wakeup,

NAND tree, EEPROM interface, CLKRUN

protocol,

mini PCI

applications, and CardBus

applications. Use the FW323 06 (128-pin) TQFP

or the FW323-T6 (120-pin) TQFP device if one or

more of these features are needed.

FW32306T100-DB Related Products

	FW32306T100-DB	L-FW32306T100
Description	Serial I/O Controller, 3 Channel(s), 50MBps, CMOS, PQFP100, TQFP-100	Serial I/O Controller, 3 Channel(s), 50MBps, CMOS, PQFP100, LEAD FREE, TQFP-100
Is it Rohs certified?	incompatible	conform to
Maker	LSC/CSI	LSC/CSI
Parts packaging code	QFP	QFP
package instruction	TQFP-100	LFQFP, QFP100,.63SQ,20
Contacts	100	100
Reach Compliance Code	compliant	compliant
Address bus width	32	32
boundary scan	NO	NO
Bus compatibility	PCI	PCI
maximum clock frequency	24.5785 MHz	24.5785 MHz
Maximum data transfer rate	50 MBps	50 MBps
External data bus width	32	32
JESD-30 code	S-PQFP-G100	S-PQFP-G100
JESD-609 code	e0	e3
length	14 mm	14 mm
low power mode	YES	YES
Number of serial I/Os	3	3
Number of terminals	100	100
Maximum operating temperature	70 °C	70 °C
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	LFQFP	LFQFP
Encapsulate equivalent code	QFP100,.63SQ,20	QFP100,.63SQ,20
Package shape	SQUARE	SQUARE
Package form	FLATPACK, LOW PROFILE, FINE PITCH	FLATPACK, LOW PROFILE, FINE PITCH
Peak Reflow Temperature (Celsius)	240	250
power supply	3.3 V	3.3 V
Certification status	Not Qualified	Not Qualified
Maximum seat height	1.6 mm	1.6 mm
Maximum supply voltage	3.6 V	3.6 V
Minimum supply voltage	3 V	3 V
Nominal supply voltage	3.3 V	3.3 V
surface mount	YES	YES
technology	CMOS	CMOS
Temperature level	COMMERCIAL	COMMERCIAL
Terminal surface	TIN LEAD	Matte Tin (Sn)
Terminal form	GULL WING	GULL WING
Terminal pitch	0.5 mm	0.5 mm
Terminal location	QUAD	QUAD
Maximum time at peak reflow temperature	30	40
width	14 mm	14 mm
uPs/uCs/peripheral integrated circuit type	SERIAL IO/COMMUNICATION CONTROLLER, SERIAL	SERIAL IO/COMMUNICATION CONTROLLER, SERIAL

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