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Z85230: DescriptionThe Zilog SCC Serial Communication Controller; File Size3MB，317 Pages; ManufacturerZilog, Inc.; Websitehttps://www.zilog.com/

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Z85230 Overview

The Zilog SCC Serial Communication Controller

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SCC™/ESCC™ U

SER

’

ANUAL

ABLE OF

ONTENTS

Chapter 1. General Description

1.1 Introduction ....................................................................................................................................

1.2 SCC’s Capabilities .........................................................................................................................

1.3 Block Diagram ...............................................................................................................................

1.4 Pin Descriptions .............................................................................................................................

1.4.1

Pins Common to both Z85X30 and Z80X30 ....................................................................

1.4.2

Pin Descriptions, (Z85X30 Only) ......................................................................................

1.4.3

Pin Descriptions, (Z80X30 Only) ......................................................................................

1-1

1-2

1-4

1-5

1-7

1-8

1-9

Chapter 2. Interfacing the SCC/ESCC

2.1 Introduction .................................................................................................................................... 2-1

2.2 Z80X30 Interface Timing ................................................................................................................ 2-1

2.2.1

Z80X30 Read Cycle Timing ............................................................................................. 2-2

2.2.2

Z80X30 Write Cycle Timing .............................................................................................. 2-3

2.2.3

Z80X30 Interrupt Acknowledge Cycle Timing .................................................................. 2-4

2.2.4

Z80X30 Register Access .................................................................................................. 2-5

2.2.5

Z80C30 Register Enhancement ....................................................................................... 2-8

2.2.6

Z80230 Register Enhancements ...................................................................................... 2-8

2.2.7

Z80X30 Reset .................................................................................................................. 2-9

2.3 Z85X30 Interface Timing ............................................................................................................. 2-10

2.3.1

Z85X30 Read Cycle Timing ........................................................................................... 2-10

2.3.2

Z85X30 Write Cycle Timing ............................................................................................ 2-11

2.3.3

Z85X30 Interrupt Acknowledge Cycle Timing ................................................................ 2-11

2.3.4

Z85X30 Register Access ................................................................................................ 2-12

2.3.5

Z85C30 Register Enhancement ..................................................................................... 2-14

2.3.6

Z85C30/Z85230 Register Enhancements ...................................................................... 2-14

2.3.7

Z85X30 Reset ................................................................................................................ 2-15

2.4 Interface Programming ................................................................................................................ 2-15

2.4.1

I/O Programming Introduction ........................................................................................ 2-15

2.4.2

Polling ............................................................................................................................ 2-16

2.4.3

Interrupts ........................................................................................................................ 2-16

2.4.4

Interrupt Control ............................................................................................................. 2-17

2.4.5

Daisy-Chain Resolution .................................................................................................. 2-19

2.4.6

Interrupt Acknowledge ................................................................................................... 2-21

2.4.7

The Receiver Interrupt ................................................................................................... 2-21

2.4.8

Transmit Interrupts and Transmit Buffer Empty Bit ........................................................ 2-25

2.4.9

External/Status Interrupts ............................................................................................... 2-31

2.5 Block/DMA Transfer ..................................................................................................................... 2-33

2.5.1

Block Transfers .............................................................................................................. 2-33

2.5.2

DMA Requests ............................................................................................................... 2-36

2.6 Test Functions ............................................................................................................................. 2-41

2.6.1

Local Loopback .............................................................................................................. 2-41

2.6.2

Auto Echo ....................................................................................................................... 2-41

SCC™/ESCC™ User’s Manual

Table of Contents

Chapter 3. SCC/ESCC Ancillary Support Circuitry

3.1 Introduction .................................................................................................................................... 3-1

3.2 Baud Rate Generator ..................................................................................................................... 3-1

3.3 Data Encoding/Decoding ............................................................................................................... 3-4

3.4 DPLL Digital Phase-Locked Loop .................................................................................................. 3-7

3.4.1

DPLL Operation in the NRZI Mode .................................................................................. 3-8

3.4.2

DPLL Operation in the FM Modes .................................................................................... 3-9

3.4.3

DPLL Operation in the Manchester Mode ...................................................................... 3-10

3.4.4

Transmit Clock Counter (ESCC only) ............................................................................. 3-10

3.5

Clock Selection ........................................................................................................................... 3-11

3.6

Crystal Oscillator ......................................................................................................................... 3-14

Chapter 4. Data Communication Modes

4.1 Introduction .................................................................................................................................... 4-1

4.1.1

Transmit Data Path Description ....................................................................................... 4-1

4.1.2

Receive Data Path Description ....................................................................................... 4-2

4.2 Asynchronous Mode ...................................................................................................................... 4-3

4.2.1

Asynchronous Transmit ................................................................................................... 4-4

4.2.2

Asynchronous Receive .................................................................................................... 4-6

4.2.3

Asynchronous Initialization ............................................................................................... 4-7

4.3 Byte-Oriented Synchronous Mode ................................................................................................. 4-8

4.3.1

Byte-Oriented Synchronous Transmit .............................................................................. 4-8

4.3.2

Byte-Oriented Synchronous Receive ............................................................................. 4-10

4.3.3

Transmitter/Receiver Synchronization ........................................................................... 4-17

4.4 Bit-Oriented Synchronous (SDLC/HDLC) Mode .......................................................................... 4-18

4.4.1

SDLC Transmit ............................................................................................................... 4-19

4.4.2

SDLC Receive ................................................................................................................ 4-22

4.4.3

SDLC Frame Status FIFO .............................................................................................. 4-27

4.4.4

SDLC Loop Mode ........................................................................................................... 4-30

Chapter 5. Register Descriptions

5.1 Introduction .................................................................................................................................... 5-1

5.2 Write Registers .............................................................................................................................. 5-2

5.2.1

Write Register 0 (Command Register) ............................................................................. 5-2

5.2.2

Write Register 1 (Transmit/Receive Interrupt and Data Transfer Mode Definition) .......... 5-4

5.2.3

Write Register 2 (Interrupt Vector) ................................................................................... 5-7

5.2.4

Write Register 3 (Receive Parameters and Control) ........................................................ 5-7

5.2.5

Write Register 4 (Transmit/Receive Miscellaneous Parameters and Modes) .................. 5-8

5.2.6

Write Register 5 (Transmit Parameters and Controls) ..................................................... 5-9

5.2.7

Write Register 6 (Sync Characters or SDLC Address Field) .......................................... 5-10

5.2.8

Write Register 7 (Sync Character or SDLC Flag) ........................................................... 5-11

5.2.9

Write Register 7 Prime (ESCC only) .............................................................................. 5-12

5.2.10 Write Register 7 Prime (85C30 only) .............................................................................. 5-13

5.2.11 Write Register 8 (Transmit Buffer) .................................................................................. 5-13

5.2.12 Write Register 9 (Master Interrupt Control) .................................................................... 5-14

5.2.13 Write Register 10 (Miscellaneous Transmitter/Receiver Control Bits) ........................... 5-15

5.2.14 Write Register 11 (Clock Mode Control) ......................................................................... 5-17

5.2.15 Write Register 12 (Lower Byte of Baud Rate Generator Time Constant) ....................... 5-18

5.2.16 Write Register 13 (Upper Byte of Baud Rate Generator Time Constant) ....................... 5-19

5.2.17 Write Register 14 (Miscellaneous Control Bits) .............................................................. 5-19

5.2.18 Write Register 15 (External/Status Interrupt Control) ..................................................... 5-20

5.3 Read Registers ............................................................................................................................ 5-21

5.3.1

Read Register 0 (Transmit/Receive Buffer Status and External Status) ........................ 5-21

5.3.2

Read Register 1 ............................................................................................................. 5-23

5.3.3

Read Register 2 ............................................................................................................. 5-24

5.3.4

Read Register 3 ............................................................................................................. 5-25

5.3.5

Read Register 4 (ESCC and 85C30 Only) ..................................................................... 5-25

5.3.6

Read Register 5 (ESCC and 85C30 Only) ..................................................................... 5-25

SCC™/ESCC™ User’s Manual

Table of Contents

5.3.7

5.3.8

5.3.9

5.3.10

5.3.11

5.3.12

5.3.13

5.3.14

5.3.15

5.3.16

Read Register 6 (Not on NMOS) ...................................................................................

Read Register 7 (Not on NMOS) ...................................................................................

Read Register 8 .............................................................................................................

Read Register 9 (ESCC and 85C30 Only) .....................................................................

Read Register 10 ...........................................................................................................

Read Register 11 (ESCC and 85C30 Only) ...................................................................

Read Register 12 ...........................................................................................................

Read Register 13 ...........................................................................................................

Read Register 14 (ESCC and 85C30 Only) ...................................................................

Read Register 15 ...........................................................................................................

5-25

5-26

5-27

Chapter 6. Application Notes

Interfacing Z80

CPUs to the Z8500 Peripheral Family ......................................................................... 6-1

The Z180™ Interfaced with the SCC at MHZ........................................................................................ 6-34

The Zilog Datacom Family with the 80186 CPU .................................................................................. 6-59

SCC in Binary Synchronous Communications ...................................................................................... 6-79

Serial Communication Controller (SCC

™

): SDLC Mode of Operation .................................................. 6-93

Using SCC with Z8000 in SDLC Protocol6-105

Boost Your System Performance Using The Zilog ESCC

™

................................................................ 6-117

Technical Considerations When Implementing LocalTalk Link Access Protocol ................................ 6-131

On-Chip Oscillator Design................................................................................................................... 6-151

Chapter 7. Questions and Answers

Zilog SCC Z8030/Z8530 Questions and Answers................................................................................... 7-1

Zilog ESCC

™

Controller Questions and Answers ................................................................................. 7-11

iii

Z85230 Related Products

	Z85230	Z8530	Z85C30
Description	The Zilog SCC Serial Communication Controller	The Zilog SCC Serial Communication Controller	The Zilog SCC Serial Communication Controller

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