Actel Corporation, Mountain View, CA 94043
© 2008 Actel Corporation. All rights reserved.
Printed in the United States of America
Part Number: 50200087-5
Release: April 2009
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holders.
Table of Contents
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Core Versions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
CorePCIF Device Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1
Functional Block Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Functional Description . . . . .
CorePCIF Master Function . .
CardBus Support . . . . . . . .
CompactPCI Hot-Swap Support
CorePCIF Backend Dataflow .
FIFO Recovery Logic . . . . . .
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13
16
18
18
18
19
2
3
Core Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Tool Flows . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
SmartDesign . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Synthesis in Libero IDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Place-and-Route in Libero IDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
4
CorePCIF Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
General Configuration Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
PCI Configuration Space Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Master/DMA Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
5
Core Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
PCI Bus Signals . . . . . . . . . . . . . . . .
Backend System-Level Signals . . . . . . . .
Backend Target and Master Dataflow Signals
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41
42
43
44
6
Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Burst Transfer at Maximum Transfer Rate . . . . . . . . . . . .
Burst Transfer with a Slow PCI Master . . . . . . . . . . . . .
Burst Transfer with a Slow Backend . . . . . . . . . . . . . . .
Backend-Terminated (BUSY) Cycle at Transfer Start (Target) .
Backend-Terminated (ERROR) Cycle at Transfer Start (Target)
PCI Interrupt Generation . . . . . . . . . . . . . . . . . . . .
Direct DMA Transfers . . . . . . . . . . . . . . . . . . . . . .
Hot-Swap Sequence . . . . . . . . . . . . . . . . . . . . . . .
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53
55
57
71
73
79
99
101
7
PCI Configuration Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Target Configuration Space
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
v3.3
3
Table of Contents
CorePCIF v3.6
8
9
Testbench Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Verification Testbench . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Implementation Hints
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
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125
125
125
126
Clocking . . . . . . . . . . . . .
Clock and Reset Networks . . . .
Assigning Pin Layout Constraints
Pin Assignments . . . . . . . . .
A PCI Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
B Synthesis Timing Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . 131
C Place-and-Route Timing Constraints . . . . . . . . . . . . . . . . . . . . . . 133
D Verification Testbench Tests . . . . . . . . . . . . . . . . . . . . . . . . . . 135
E VHDL User Testbench Procedures . . . . . . . . . . . . . . . . . . . . . . . 137
F Verilog User Testbench Procedures . . . . . . . . . . . . . . . . . . . . . . . 139
G Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
Ordering Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
H List of Document Changes . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
I
Product Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
Customer Service . . . . . . . . . . . . . . . . . .
Actel Customer Technical Support Center . . . . .
Actel Technical Support . . . . . . . . . . . . . .
Website . . . . . . . . . . . . . . . . . . . . . . .
Contacting the Customer Technical Support Center
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145
145
145
145
145
Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
4
v3.3
Introduction
CorePCIF connects memory, FIFO, and processor subsystem resources to the main system via the PCI bus. CorePCIF
is intended for use with a wide variety of peripherals where high-performance data transactions are required.
Figure 1
depicts typical system applications using the core. Though CorePCIF can handle any transfer rate, most applications
will operate with zero wait states. When required, wait states can be inserted automatically by a slower peripheral.
CorePCIF can implement Target and/or Master functions. The Target function allows the PCI bus to access memory
devices attached to the CorePCIF backend. The Master function allows CorePCIF to move data between the backend
or internal registers and the PCI bus using the internal DMA engine. The DMA engine can be programmed either
from the PCI bus or directly from the backend.
CorePCIF can be customized. A variety of parameters are provided to easily change features such as memory and I/O
sizes along with the PCI vendor and device IDs. A single top-level core has parameters that enable and disable
functions, allowing a minimal-size core to be implemented for the required functionality. The core consists of four basic
units: the Target controller, the Master controller, the DMA controller, and the backend controller. The backend
controller provides the necessary control for the I/O or memory subsystem, allowing external (to the core) memory and
FIFOs to be directly connected to the core.
FRAMEN
REQ64N
IRDYN
DEVSELN
ACK64N
TRDYN
SERRN
IDSEL
AD
PAR
PAR64
CBE
PERRN
INTAN
REQN
GNTN
CLK
RSTN
STOPN
Master Control Signals
Backend
Controller
System CPU
Memory Control Signals
MEM_ADDRESS BUS
Memory
Subsystem
MEM_DATA BUS
CorePCIF
Target+Master
Controller
PCI Bus
Master
Bridge
Target
Figure 1 · CorePCIF System Block Diagram
v3.3
5
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