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74LVCH322244AEC

Description
Buffers and Line Drivers 32-bit 5V tol I/O buffer 3-S 3
Categorylogic    logic   
File Size373KB,74 Pages
ManufacturerNXP
Websitehttps://www.nxp.com
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74LVCH322244AEC Overview

Buffers and Line Drivers 32-bit 5V tol I/O buffer 3-S 3

74LVCH322244AEC Parametric

Parameter NameAttribute value
Is it lead-free?Contains lead
Is it Rohs certified?incompatible
MakerNXP
Parts packaging codeBGA
package instructionLFBGA, BGA96,6X16,32
Contacts96
Manufacturer packaging codeSOT-536-1
Reach Compliance Code_compli
Control typeENABLE LOW
seriesLVC/LCX/Z
JESD-30 codeR-PBGA-B96
JESD-609 codee0
length13.5 mm
Logic integrated circuit typeBUS DRIVER
MaximumI(ol)0.012 A
Humidity sensitivity level4
Number of digits4
Number of functions8
Number of ports2
Number of terminals96
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
Output characteristics3-STATE WITH SERIES RESISTOR
Output polarityTRUE
Package body materialPLASTIC/EPOXY
encapsulated codeLFBGA
Encapsulate equivalent codeBGA96,6X16,32
Package shapeRECTANGULAR
Package formGRID ARRAY, LOW PROFILE, FINE PITCH
Peak Reflow Temperature (Celsius)240
power supply3.3 V
Prop。Delay @ Nom-Su6.3 ns
propagation delay (tpd)6.7 ns
Certification statusNot Qualified
Maximum seat height1.5 mm
Maximum supply voltage (Vsup)3.6 V
Minimum supply voltage (Vsup)1.2 V
Nominal supply voltage (Vsup)2.7 V
surface mountYES
technologyCMOS
Temperature levelINDUSTRIAL
Terminal surfaceTin/Lead (Sn63Pb37)
Terminal formBALL
Terminal pitch0.8 mm
Terminal locationBOTTOM
Maximum time at peak reflow temperature20
width5.5 mm
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LPC3141/3143
Rev. 0.16 — 27 May 2010
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Low-cost, low-power ARM926EJ microcontrollers with USB
High-speed OTG, SD/MMC, and NAND flash controller
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Preliminary data sheet
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1. General description
The NXP LPC3141/3143 combine a 270 MHz ARM926EJ-S CPU core, High-speed USB
2.0 OTG, 192 KB SRAM, NAND flash controller, flexible external bus interface, four
channel 10-bit A/D, and a myriad of serial and parallel interfaces in a single chip targeted
at consumer, industrial, medical, and communication markets. To optimize system power
consumption, the LPC3141/3143 have multiple power domains and a very flexible Clock
Generation Unit (CGU) that provides dynamic clock gating and scaling.
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2. Features and benefits
2.1 Key features
CPU platform
270 MHz, 32-bit ARM926EJ-S
16 kB D-cache and 16 kB I-cache
Memory Management Unit (MMU)
Internal memory
192 kB embedded SRAM
External memory interface
NAND flash controller with 8-bit ECC and AES decryption support (LPC3143 only)
8/16-bit Multi-Port Memory Controller (MPMC): SDRAM and SRAM
Security
AES decryption engine (LPC3143 only)
Secure one-time programmable memory for AES key storage and customer use
128 bit unique ID per device for DRM schemes
Communication and connectivity
High-speed USB 2.0 (OTG, Host, Device) with on-chip PHY
Two I
2
S interfaces
Integrated master/slave SPI
Two master/slave I
2
C-bus interfaces
Fast UART
Memory Card Interface (MCI): MMC/SD/SDIO/CE-ATA
Four-channel 10-bit ADC
Integrated 4/8/16-bit 6800/8080 compatible LCD interface
System functions
Dynamic clock gating and scaling
Multiple power domains
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