Philips Semiconductors
Product specification
Octal buffer/line driver with 5 V tolerant
inputs/outputs; inverting; 3-state
FEATURES
•
5 V tolerant inputs/outputs for interfacing with 5 V logic
•
Supply voltage range from 1.2 to 3.6 V
•
CMOS low power consumption
•
Direct interface with TTL levels
•
Inputs accept voltages up to 5.5 V
•
High-impedance when V
CC
= 0 V
•
Complies with JEDEC standard no. 8-1A
•
ESD protection:
HBM EIA/JESD22-A114-A exceeds 2000 V
MM EIA/JESD22-A115-A exceeds 200 V.
•
Specified from
−40
to +85
°C
and
−40
to +125
°C.
DESCRIPTION
74LVC240A
The 74LVC240A is a high-performance, low-power,
low-voltage, Si-gate CMOS device, superior to most
advanced CMOS compatible TTL families.
Inputs can be driven from either 3.3 or 5 V devices.
In 3-state operation, outputs can handle 5 V. These
features allow the use of these devices as translators in a
mixed 3.3 and 5 V environment.
The 74LVC240A is an octal non-inverting buffer/line driver
with 3-state outputs. The 3-state outputs are controlled by
the output enable inputs 1OE and 2OE. A HIGH on nOE
causes the outputs to assume a high-impedance
OFF-state. Schmitt-trigger action at all inputs makes the
circuit highly tolerant for slower input rise and fall times.
The 74LVC240A is functionally identical to the
74LVC244A, which has non-inverting outputs.
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25
°C;
t
r
= t
f
≤
2.5 ns.
SYMBOL
t
PHL
/t
PLH
t
PZH
/t
PZL
t
PHZ
/t
PLZ
C
I
C
PD
PARAMETER
propagation delay nAn to nYn
3-state output enable time nOE to nYn
3-state output disable time nOE to nYn
input capacitance
power dissipation capacitance per buffer
V
CC
= 3.3 V; notes 1 and 2
outputs enabled
outputs disabled
Notes
1. C
PD
is used to determine the dynamic power dissipation (P
D
in
µW).
P
D
= C
PD
×
V
CC2
×
f
i
×
N +
Σ(C
L
×
V
CC2
×
f
o
) where:
f
i
= input frequency in MHz;
f
o
= output frequency in MHz;
C
L
= output load capacitance in pF;
V
CC
= supply voltage in Volts;
N = total load switching outputs;
Σ(C
L
×
V
CC2
×
f
o
) = sum of the outputs.
2. The condition is V
I
= GND to V
CC
.
10
3.0
pF
pF
CONDITIONS
C
L
= 50 pF; V
CC
= 3.3 V
C
L
= 50 pF; V
CC
= 3.3 V
C
L
= 50 pF; V
CC
= 3.3 V
TYPICAL
3.5
4.3
3.7
5.0
ns
ns
ns
pF
UNIT
2003 Dec 02
2
Philips Semiconductors
Product specification
Octal buffer/line driver with 5 V tolerant
inputs/outputs; inverting; 3-state
74LVC240A
handbook, halfpage
1OE
1
VCC
20
19
18
17
16
2OE
1Y0
2A0
1Y1
2A1
1Y2
2A2
1Y3
handbook, halfpage
1OE 1
1A0 2
2Y0 3
1A1 4
2Y1 5
20 VCC
19 2OE
18 1Y0
17 2A0
16 1Y1
1A0
2Y0
1A1
2Y1
1A2
2Y2
2
3
4
5
240
1A2 6
2Y2 7
1A3 8
2Y3 9
GND 10
MGU777
15 2A1
14 1Y2
GND
(1)
6
7
8
9
10
Top view
GND
11
2A3
MBL761
15
14
13
12
13 2A2
12 1Y3
11 2A3
1A3
2Y3
(1) The die substrate is attached to this pad using conductive die
attach material. It can not be used as a supply pin or input.
Fig.1 Pin configuration SO20 and (T)SSOP20.
Fig.2 Pin configuration DHVQFN20.
handbook, halfpage
1
EN
18
16
14
12
handbook, halfpage
2
1A0
2A0
1A1
2A1
1A2
2A2
1A3
2A3
1OE
2OE
17
4
15
6
13
8
11
1
19
1Y0 18
2Y0 3
1Y1 16
2Y1 5
1Y2 14
2Y2
7
2
4
6
8
19
EN
9
7
5
3
MGU778
1Y3 12
2Y3 9
11
13
MGU779
15
17
Fig.3 Logic symbol.
Fig.4 Logic symbol (IEEE/IEC).
2003 Dec 02
4
Philips Semiconductors
Product specification
Octal buffer/line driver with 5 V tolerant
inputs/outputs; inverting; 3-state
74LVC240A
handbook, halfpage
2
1A0
1Y0
18
4
1A1
1Y1
16
6
1A2
1Y2
14
8
1A3
1Y3
12
1
1OE
17
2A0
2Y0
3
15
2A1
2Y1
5
13
2A2
2Y2
7
11
2A3
2Y3
9
19
2OE
MGU780
Fig.5 Functional diagram.
RECOMMENDED OPERATING CONDITIONS
SYMBOL
V
CC
V
I
V
O
T
amb
t
r
, t
f
PARAMETER
supply voltage
input voltage
output voltage
ambient temperature
input rise and fall times
output HIGH or LOW state
output 3-state
in free air
V
CC
= 1.2 to 2.7 V
V
CC
= 2.7 to 3.6 V
CONDITIONS
for maximum speed performance
for low voltage applications
MIN.
2.7
1.2
0
0
0
−40
0
0
MAX.
3.6
3.6
5.5
V
CC
5.5
+125
20
10
V
V
V
V
V
°C
ns/V
ns/V
UNIT
2003 Dec 02
5
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