MC74VHC50
Hex Buffer
The MC74VHC50 is an advanced high speed CMOS buffer
fabricated with silicon gate CMOS technology.
The internal circuit is composed of three stages, including a buffered
output which provides high noise immunity and stable output. The
inputs tolerate voltages up to 7 V, allowing the interface of 5 V systems
to 3 V systems.
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•
•
•
•
•
•
•
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High Speed: t
PD
= 3.8 ns (Typ) at V
CC
= 5 V
Low Power Dissipation: I
CC
= 2
mA
(Max) at T
A
= 25°C
High Noise Immunity: V
NIH
= V
NIL
= 28% V
CC
Power Down Protection Provided on Inputs
Balanced Propagation Delays
Designed for 2 V to 5.5 V Operating Range
Low Noise: V
OLP
= 0.8 V (Max)
These devices are available in Pb-
-free package(s). Specifications herein
apply to both standard and Pb-
-free devices. Please see our website at
www.onsemi.com for specific Pb-
-free orderable part numbers, or
contact your local ON Semiconductor sales office or representative.
14-
-LEAD SOIC
D SUFFIX
CASE 751A
14-
-LEAD TSSOP
DT SUFFIX
CASE 948G
14-
-LEAD SOIC EIAJ
M SUFFIX
CASE 965
PIN CONNECTION AND
MARKING DIAGRAM
(Top View)
V
CC
14
A6
13
Y6
12
A5
11
Y5
10
A4
9
Y4
8
1
A1
1
2
Y1
A1
2
Y1
3
A2
4
Y2
5
A3
6
Y3
7
GND
A2
3
4
Y2
A1
Y3
Y=A
A2
A3
A4
Y5
A5
1
1
1
1
1
1
Y1
Y2
Y3
Y4
Y5
Y6
For detailed package marking information, see the Marking
Diagram section on page 4 of this data sheet.
A3
5
6
FUNCTION TABLE
A Input
L
H
Y Output
L
H
A4
9
8
Y4
A5
11
10
ORDERING INFORMATION
Device
MC74VHC50D
Package
SOIC
SOIC EIAJ
Shipping
55 Units/Rail
50 Units/Rail
A6
13
12
Y6
A6
Figure 1. Logic Diagram
Figure 2. Logic Symbol
MC74VHC50M
©
Semiconductor Components Industries, LLC, 2006
March, 2006 - Rev. 4
-
1
Publication Order Number:
MC74VHC50/D
MC74VHC50
MAXIMUM RATINGS
Symbol
V
CC
V
IN
V
OUT
I
IK
I
OK
I
OUT
I
CC
T
STG
T
L
T
J
θ
JA
DC Supply Voltage
DC Input Voltage
DC Output Voltage
DC Input Diode Current
DC Output Diode Current
DC Output Sink Current
DC Supply Current per Supply Pin
Storage Temperature Range
Lead Temperature, 1 mm from Case for 10 Seconds
Junction Temperature under Bias
Thermal Resistance
(Note 1)
SOIC
TSSOP
Oxygen Index: 30 to 35
Human Body Model (Note 2)
Machine Model (Note 3)
Charged Device Model (Note 4)
Above V
CC
and Below GND at 85°C (Note 5)
V
I
< GND
V
O
< GND
Parameter
Value
−0.5
to
+7.0
−0.5
to
+7.0
−0.5
to V
CC
+0.5
−20
±20
±25
±50
−65
to
+150
260
+150
125
170
Level 1
UL 94 V--0 @ 0.125 in
> 2000
> 200
2000
±300
V
Unit
V
V
V
mA
mA
mA
mA
°C
°C
°C
°C/W
MSL
F
R
V
ESD
Moisture Sensitivity
Flammability Rating
ESD Withstand Voltage
I
Latch--Up
Latch--Up Performance
mA
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. Measured with minimum pad spacing on an FR4 board, using 10 mm--by--1 inch, 2--ounce copper trace with no air flow.
2. Tested to EIA/JESD22--A114--A.
3. Tested to EIA/JESD22--A115--A.
4. Tested to JESD22--C101--A.
5. Tested to EIA/JESD78.
RECOMMENDED OPERATING CONDITIONS
Symbol
V
CC
V
I
V
O
T
A
Δt/ΔV
Supply Voltage
Input Voltage
Output Voltage
Operating Free--Air Temperature
Input Transition Rise or Fall Rate
V
CC
= 3.0 V
±0.3
V
V
CC
= 5.0 V
±0.5
V
(Note 6)
(HIGH or LOW State)
Parameter
Min
2.0
0
0
−55
0
0
Max
5.5
5.5
V
CC
+125
100
20
Unit
V
V
V
°C
ns/V
6. Unused inputs may not be left open. All inputs must be tied to a high-- or low--logic input voltage level.
NOTE:
The
θ
JA
of the package is equal to 1/Derating. Higher junction temperatures may affect the expected lifetime of the device per the table
and figure below.
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2
MC74VHC50
DC ELECTRICAL CHARACTERISTICS
V
CC
Symbol
V
IH
Parameter
Minimum High--Level
Input Voltage
Test Conditions
(V)
2.0
3.0
4.5
5.5
2.0
3.0
4.5
5.5
V
IN
= V
IH
or V
IL
I
OH
= --50
mA
V
IN
= V
IH
or V
IL
I
OH
= --4 mA
I
OH
= --8 mA
V
OL
Maximum Low--Level
Output Voltage
V
IN
= V
IH
or V
IL
V
IN
= V
IH
or V
IL
I
OL
= 50
mA
V
IN
= V
IH
or V
IL
I
OL
= 4 mA
I
OL
= 8 mA
I
IN
I
CC
Maximum Input
Leakage Current
Maximum Quiescent
Supply Current
V
IN
= 5.5 V or GND
V
IN
= V
CC
or GND
2.0
3.0
4.5
3.0
4.5
2.0
3.0
4.5
3.0
4.5
0 to
5.5
5.5
1.9
2.9
4.4
2.58
3.94
0.0
0.0
0.0
0.1
0.1
0.1
0.36
0.36
±0.1
2.0
2.0
3.0
4.5
Min
1.5
2.0
3.15
3.85
0.5
0.9
1.35
1.65
1.9
2.9
4.4
2.48
3.80
0.1
0.1
0.1
0.44
0.44
±1.0
20
T
A
= 25°C
Typ
Max
T
A
≤
85°C
Min
1.5
2.0
3.15
3.85
0.5
0.9
1.35
1.65
1.9
2.9
4.4
2.34
3.66
0.1
0.1
0.1
0.52
0.52
±1.0
40
Max
T
A
≤
125°C
Min
1.5
2.0
3.15
3.85
0.5
0.9
1.35
1.65
Max
Unit
V
V
IL
Maximum Low--Level
Input Voltage
V
V
OH
Minimum High--Level
Output Voltage
V
IN
= V
IH
or V
IL
V
V
V
V
mA
mA
AC ELECTRICAL CHARACTERISTICS
(C
load
= 50 pF, Input t
r
= t
f
= 3.0 ns)
T
A
= 25°C
Symbol
t
PLH
,
t
PHL
Parameter
Maximum
Propogation Delay,
Input A to Y
Test Conditions
V
CC
= 3.0
±
0.3 V
V
CC
= 5.0
±
0.5 V
C
L
= 15 pF
C
L
= 50 pF
C
L
= 15 pF
C
L
= 50 pF
Min
Typ
5.0
7.5
3.8
5.3
4
Max
7.1
10.6
5.5
7.5
10
T
A
≤
85°C
Min
Max
8.5
12.0
6.5
8.5
10
T
A
≤
125°C
Min
Max
10.0
14.5
8.0
10.0
10
pF
Unit
ns
C
IN
Maximum Input
Capacitance
Typical @ 25°C, V
CC
= 5.0 V
18
C
PD
Power Dissipation Capacitance (Note 7)
pF
7. C
PD
is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load.
Average operating current can be obtained by the equation: I
CC(OPR
)
= C
PD
¯
V
CC
¯
f
in
+ I
CC
. C
PD
is used to determine the no--load dynamic
power consumption; P
D
= C
PD
¯
V
CC2
¯
f
in
+ I
CC
¯
V
CC
.
NOISE CHARACTERISTICS
(Input t
r
= t
f
= 3.0 ns, C
L
= 50 pF, V
CC
= 5.0 V)
T
A
= 25°C
Symbol
V
OLP
V
OLV
V
IHD
V
ILD
Characteristic
Quiet Output Maximum Dynamic V
OL
Quiet Output Minimum Dynamic V
OL
Minimum High Level Dynamic Input Voltage
Maximum Low Level Dynamic Input Voltage
Typ
0.8
--0.8
Max
1.0
--1.0
3.5
1.5
Unit
V
V
V
V
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3
MC74VHC50
TEST POINT
V
CC
A
50%
t
PLH
50% V
CC
*Includes all probe and jig capacitance
t
PHL
GND
DEVICE
UNDER
TEST
OUTPUT
C
L
*
Y
Figure 3. Switching Waveforms
Figure 4. Test Circuit
INPUT
Figure 5. Input Equivalent Circuit
MARKING DIAGRAMS
(Top View)
14
13
12
11
10
9
8
14 13 12 11 10
9
8
VHC50
AWLYWW*
1
2
3
4
5
6
7
1
2
3
VHC
50
ALYW*
4
5
6
7
14-
-LEAD SOIC
D SUFFIX
CASE 751A
14
13
12
11
10
9
8
14-
-LEAD TSSOP
DT SUFFIX
CASE 948G
VHC50
ALYW*
1
2
3
4
5
6
7
14-
-LEAD SOIC EIAJ
M SUFFIX
CASE 965
*See Applications Note #AND8004/D for date code and traceability information.
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4
MC74VHC50
PACKAGE DIMENSIONS
SOIC-
-14
D SUFFIX
CASE 751A--03
ISSUE F
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
- -
-A-
14
8
- -
-B-
1
7
P
7 PL
0.25 (0.010)
M
B
M
G
C
R
X 45
_
F
- -
-T-
SEATING
PLANE
D
14 PL
0.25 (0.010)
M
K
T B
S
M
A
S
J
DIM
A
B
C
D
F
G
J
K
M
P
R
MILLIMETERS
MIN
MAX
8.55
8.75
3.80
4.00
1.35
1.75
0.35
0.49
0.40
1.25
1.27 BSC
0.19
0.25
0.10
0.25
0
_
7
_
5.80
6.20
0.25
0.50
INCHES
MIN
MAX
0.337
0.344
0.150
0.157
0.054
0.068
0.014
0.019
0.016
0.049
0.050 BSC
0.008
0.009
0.004
0.009
0
_
7
_
0.228
0.244
0.010
0.019
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