Preliminary W24100
128K
×
8 CMOS STATIC RAM
GENERAL DESCRIPTION
The W24100 is a normal-speed, very low-power CMOS static RAM organized as 131072
×
8 bits that
operates on a single 5-volt power supply. This device is manufactured using Winbond's high
performance CMOS technology.
FEATURES
•
•
•
•
•
•
Low power consumption:
−
Active: 385 mW (max.)
Access time: 70 nS
Single 5V power supply
Fully static operation
All inputs and outputs directly TTL compatible
Three-state outputs
•
•
•
Battery back-up operation capability
Data retention voltage: 2V (min.)
Packaged in 32-pin 600 mil DIP, 450 mil SOP,
standard type one TSOP (8 mm
×
20 mm) and
small type one TSOP (8 mm
×
13.4 mm)
PIN CONFIGURATIONS
BLOCK DIAGRAM
CLK GEN.
A16
PRECHARGE CKT.
NC
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O1
I/O2
I/O3
V
SS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
V
DD
A15
CS2
WE
A13
A8
A9
A11
OE
A10
CS1
I/O 8
I/O 7
I/O 6
I/O5
I/O4
A14
A12
A4
A3
A2
A7
A6
A5
A9
I/O1
:
I/O8
DATA
CNTRL.
CLK
GEN.
WE
CS1
CS2
OE
A15 A13 A8 A1 A0 A11A10
I/O CKT.
COLUMN DECODER
D
E
C
O
D
E
R
R
O
W
CORE CELL ARRAY
1024 ROWS
128 X 8 COLUMNS
32-pin
SOP
25
24
23
22
21
20
19
18
17
PIN DESCRIPTION
SYMBOL
A0−A16
I/O1−I/O8
CS1, CS2
WE
OE
V
DD
V
SS
NC
DESCRIPTION
Address Inputs
Data Inputs/Outputs
Chip Select Input
Write Enable Input
Output Enable Input
Power Supply
Ground
No Connection
A11
A9
A8
A13
WE
CS2
A15
V
DD
NC
A16
A14
A12
A7
A6
A5
A4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32-pin
TSOP
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
OE
A10
CS1
I/O8
I/O7
I/O6
I/O5
I/O4
V
SS
I/O3
I/O2
I/O1
A0
A1
A2
A3
-1-
Publication Release Date: October 1999
Revision A1
Preliminary W24100
TRUTH TABLE
CS1
H
X
CS2
X
L
H
H
H
OE
X
X
WE
X
X
MODE
Not Selected
Not Selected
Output Disable
Read
Write
L
L
L
H
L
X
H
H
L
I/O1−I/O8
High Z
High Z
High Z
Data Out
Data In
V
DD
CURRENT
I
SB
, I
SB
1
I
SB
, I
SB
1
I
DD
I
DD
I
DD
DC CHARACTERISTICS
Absolute Maximum Ratings
PARAMETER
Supply Voltage to V
SS
Potential
Input/Output to V
SS
Potential
Allowable Power Dissipation
Storage Temperature
Operating Temperature
RATING
-0.5 to +7.0
-0.5 to V
DD
+0.5
1.0
-65 to +150
0 to 70
UNIT
V
V
W
°C
°C
Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the
device.
Operating Characteristics
(V
DD
= 5V
±10%;
V
SS
= 0V; T
A
= 0° C to 70° C)
PARAMETER
Input Low Voltage
Input High Voltage
Input Leakage Current
Output Leakage
Current
SYM.
V
IL
V
IH
I
LI
I
LO
TEST CONDITIONS
-
-
V
IN
= V
SS
to V
DD
V
I/O
= V
SS
to V
DD,
CS1 = V
IH
(min.) or
OE
= V
IH
(min.)
or WE = V
IL
(max.)
I
OL
= +2.1 mA
I
OH
= -1.0 mA
CS1
= V
IL
(max.) and
CS2 = V
IH
(min.), I/O = 0 mA
Cycle = min., Duty = 100%
MIN.
-0.5
+2.2
-1
-1
TYP.*
-
-
-
-
MAX.
+0.8
V
DD
+0.5
+1
+1
UNIT
V
V
µA
µA
Output Low Voltage
Output High Voltage
Operating Power
Supply Current
Standby Power Supply
Current
V
OL
V
OH
I
DD
-
2.4
-
-
-
-
0.4
-
70
V
V
mA
I
SB
I
SB
1
CS = V
IH
(min.), Cycle = min.
Duty = 100%
LL
CS1
≥
V
DD
-0.2V or
CS2
≤
0.2V
L
-
-
-
-
-
3
50
mA
µA
-
100
Note: Typical parameter is measured under ambient temperature T
A
= 25° C and V
DD
= 5V.
-2-
Preliminary W24100
CAPACITANCE
(V
DD
= 5 V, T
A
= 25° C, f = 1 MHz)
PARAMETER
Input Capacitance
Input/Output Capacitance
SYM.
C
IN
C
I/O
CONDITIONS
V
IN
= 0V
V
OUT
= 0V
MAX.
6
8
UNIT
pF
pF
Note: These parameters are sampled but not 100% tested.
AC CHARACTERISTICS
AC Test Conditions
PARAMETER
Input Pulse Levels
Input Rise and Fall Times
Input and Output Timing Reference Level
Output Load
0V to 3.0V
5 nS
1.5V
See the drawing below
CONDITIONS
AC Test Loads and Waveform
1 TTL
OUTPUT
100 pF
Including
Jig and
Scope
OUTPUT
1 TTL
5 pF
Including
Jig and
Scope
(For T
CLZ,
T
OLZ,
T
CHZ,
T
OHZ,
T
WHZ,
T
OW
)
3.0V
0V
5 nS
90%
10%
90%
10%
5 nS
-3-
Publication Release Date: October 1999
Revision A1
Preliminary W24100
AC Characteristics, continued
(V
DD
= 5V
±10%;
V
SS
= 0V; T
A
= 0° C to 70° C)
Read Cycle
PARAMETER
SYM.
W24100-70L
MIN.
Read Cycle Time
Address Access Time
Chip Select Access Time
Output Enable to Output Valid
Chip Selection to Output in Low Z
Output Enable to Output in Low Z
Chip Deselection to Output in High Z
Output Disable to Output in High Z
Output Hold from Address Change
∗
These parameters are sampled but not 100% tested
W24100-70LL
MIN.
70
-
-
-
10
5
-
-
10
MAX.
-
70
70
35
-
-
30
30
-
UNIT
MAX.
-
70
70
35
-
-
30
30
-
T
RC
T
AA
T
ACS
T
AOE
T
CLZ
*
T
OLZ
*
T
CHZ
*
T
OHZ
*
T
OH
70
-
-
-
10
5
-
-
10
nS
nS
nS
nS
nS
nS
nS
nS
nS
Write Cycle
PARAMETER
SYM.
W24100-70L
MIN.
Write Cycle Time
Chip Selection to End of Write
Address Valid to End of Write
Address Setup Time
Write Pulse Width
Write Recovery Time
CS1
, CS2, WE
W24100-70LL
MIN.
70
50
50
0
50
0
30
0
-
-
5
MAX.
-
-
-
-
-
-
-
-
25
25
-
UNIT
MAX.
-
-
-
-
-
-
-
-
25
25
-
T
WC
T
CW
T
AW
T
AS
T
WP
T
WR
T
DW
T
DH
T
WHZ
*
T
OHZ
*
T
OW
70
50
50
0
50
0
30
0
-
-
5
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
Data Valid to End of Write
Data Hold from End of Write
Write to Output in High Z
Output Disable to Output in High Z
Output Active from End of Write
∗
These parameters are sampled but not 100% tested
-4-
Preliminary W24100
TIMING WAVEFORMS
Read Cycle 1
(Address Controlled)
T
RC
Address
T
OH
D
OUT
T
AA
T
OH
Read Cycle 2
(Chip Select Controlled)
CS1
CS2
T
ACS
T
CLZ
D
OUT
T
CHZ
Read Cycle 3
(Output Enable Controlled)
T
RC
Address
T
AA
OE
T
AOE
T
OLZ
CS1
T
OH
CS2
T
ACS
D
OUT
T
CLZ
T
CHZ
T
OHZ
-5-
Publication Release Date: October 1999
Revision A1
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