Philips Semiconductors
Preliminary specification
96 kHz IEC 958 audio DAC
CONTENTS
1
1.1
1.2
1.3
1.4
1.5
2
3
4
5
6
7
8
8.1
8.2
8.3
8.4
8.5
8.5.1
8.5.2
8.5.3
8.5.4
8.5.5
8.5.6
8.6
8.6.1
8.6.2
8.7
8.7.1
8.7.2
8.7.3
8.7.4
8.7.5
8.7.6
8.7.7
8.7.8
8.7.9
FEATURES
General
Control
IEC 958 input
Digital output and input interfaces
Digital sound processing and DAC
APPLICATIONS
GENERAL DESCRIPTION
QUICK REFERENCE DATA
ORDERING INFORMATION
BLOCK DIAGRAM
PINNING
FUNCTIONAL DESCRIPTION
Operating modes
Clock regeneration and lock detection
Mute
Auto mute
Data path
IEC 958 input
Digital data output and input interface
Audio feature processor
Interpolator
Noise shaper
The Filter Stream DAC (FSDAC)
Control
Static pin control mode
L3 control mode
L3 interface
General
Device addressing
Register addressing
Data write mode
Data read mode
Initialization string
Overview of L3 interface registers
Writable registers
Readable registers
16
17
9
10
11
12
13
14
15
15.1
15.2
15.3
15.4
15.5
LIMITING VALUES
UDA1351H
THERMAL CHARACTERISTICS
CHARACTERISTICS
TIMING CHARACTERISTICS
APPLICATION INFORMATION
PACKAGE OUTLINE
SOLDERING
Introduction to soldering surface mount
packages
Reflow soldering
Wave soldering
Manual soldering
Suitability of surface mount IC packages for
wave and reflow soldering methods
DEFINITIONS
LIFE SUPPORT APPLICATIONS
2000 Feb 18
2
Philips Semiconductors
Preliminary specification
96 kHz IEC 958 audio DAC
1
1.1
FEATURES
General
UDA1351H
•
2.7 to 3.6 V power supply
•
Integrated digital filter and Digital-to-Analog
Converter (DAC)
•
Master-mode data output interface for off-chip sound
processing
•
256f
s
system clock output
•
20-bit data-path in interpolator
•
High performance
•
No analog post filtering required for DAC
•
Supports sampling frequencies from 28 up to 100 kHz
•
The UDA1351H is fully pin and function compatible with
the UDA1350AH.
1.2
Control
1.5
Digital sound processing and DAC
•
Pre-emphasis information of IEC 958 input bitstream
available in L3 interface register and on pins
•
Automatic de-emphasis when using IEC 958 input with
32.0, 44.1 and 48.0 kHz audio sample frequencies
•
Soft mute by means of a cosine roll-off circuit selectable
via pin MUTE or the L3 interface
•
Interpolating filter (f
s
to 128f
s
) by means of a cascade of
a recursive filter and a FIR filter
•
Third-order noise shaper operating at 128f
s
generates
bitstream for the DAC
•
Filter stream digital-to-analog converter.
2
APPLICATIONS
•
Controlled either by means of static pins or via the
L3 microcontroller interface.
1.3
IEC 958 input
•
On-chip amplifier for converting IEC 958 input to CMOS
levels
•
Selectable IEC 958 input channel, one out of two
•
Lock indication signal available on pin LOCK
•
Lock indication signal combined on-chip with the Pulse
Code Modulation (PCM) status bit; in case non-PCM
has been detected pin LOCK indicates out-of-lock
•
Key channel-status bits available via L3 interface (lock,
pre-emphasis, audio sample frequency, 2 channel PCM
indication and clock accuracy).
1.4
Digital output and input interfaces
•
Digital audio systems.
3
GENERAL DESCRIPTION
The UDA1351H is a single chip IEC 958 audio decoder
with an integrated stereo digital-to-analog converter
employing bitstream conversion techniques.
Besides the UDA1351H, which is the full featured version
in QFP44 package, there also exists the UDA1351TS.
The UDA1351TS has IEC 958 input to the DAC only and
is in SSOP28 package.
The UDA1351H can operate in various operating modes:
•
IEC 958 input to the DAC including on-chip signal
processing
•
IEC 958 input via the digital data output interface to the
external Digital Signal Processor (DSP)
•
IEC 958 input to the DAC and a DSP
•
IEC 958 input via a DSP to the DAC including on-chip
signal processing
•
External source data input to the DAC including on-chip
signal processing.
•
When the UDA1351H is clock master of the data output
interfaces:
– BCKO and WSO signals are output
– I
2
S-bus or LSB-justified 16, 20 and 24 bits formats
are supported.
•
When the UDA1351H is clock slave of the data input
interface:
– BCK and WS signals are input
– I
2
S-bus or LSB-justified 16, 20 and 24 bits formats
are supported.
2000 Feb 18
3
Philips Semiconductors
Preliminary specification
96 kHz IEC 958 audio DAC
The IEC 958 input audio data including the accompanying
pre-emphasis information is available on the output data
interface.
A lock indication signal is available on pin LOCK indicating
that the IEC 958 decoder is locked.
4
QUICK REFERENCE DATA
SYMBOL
Supplies
V
DDD
V
DDA
I
DDA(DAC)
I
DDA(PLL)
I
DDD(C)
I
DDD
P
digital supply voltage
analog supply voltage
analog supply current of DAC
analog supply current of PLL
digital supply current of core
digital supply current
power consumption at 48 kHz
power consumption at 96 kHz
General
t
rst
T
amb
V
o(rms)
(THD + N)/S
reset active time
ambient temperature
−
−40
note 1
−
250
−
900
−90
−60
−85
−58
100
100
96
0.1
power-on
power-down
at 48 kHz
at 96 kHz
at 48 kHz
at 96 kHz
at 48 kHz
at 96 kHz
DAC in playback mode
DAC in playback mode
2.7
2.7
−
−
−
−
−
−
−
−
−
−
3.0
3.0
8.0
750
0.7
1.0
16.0
24.5
2.0
3.0
80
58
109
87
PARAMETER
CONDITIONS
MIN.
UDA1351H
By default the DAC output and the data output interface
are muted when the decoder is out-of-lock. However, this
setting can be overruled in the L3 control mode.
TYP.
MAX.
UNIT
3.6
3.6
−
−
−
−
−
−
−
−
−
−
−
−
−
+85
−
−85
−55
−80
−53
−
−
−
−
V
V
mA
µA
mA
mA
mA
mA
mA
mA
mW
mW
mW
mW
µs
°C
mV
dB
dB
dB
dB
dB
dB
dB
dB
DAC in Power-down mode
−
DAC in Power-down mode
−
Digital-to-analog converter
output voltage (RMS value)
total harmonic distortion-plus-noise to f
i
= 1.0 kHz tone at 48 kHz
signal ratio
at 0 dB
−
at
−40
dB; A-weighted
f
i
= 1.0 kHz tone at 96 kHz
at 0 dB
at
−40
dB; A-weighted
S/N
signal-to-noise ratio at 48 kHz
signal-to-noise ratio at 96 kHz
α
cs
∆V
o
Note
1. The DAC output voltage is proportionally to the DAC power supply voltage.
2000 Feb 18
4
channel separation
unbalance of output voltages
f
i
= 1.0 kHz tone;
code = 0; A-weighted
f
i
= 1.0 kHz tone;
code = 0; A-weighted
f
i
= 1.0 kHz tone
f
i
= 1.0 kHz tone
−
−
95
95
−
0.4
−
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