TC4027BF datasheet, PDF - EEWORLD Datasheet

TC4027BF: Descriptiondual J-K master-slave flip flop; Categorylogic logic; File Size269KB，7 Pages; ManufacturerToshiba Semiconductor; Websitehttp://toshiba-semicon-storage.com/

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TC4027BF Overview

dual J-K master-slave flip flop

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	incompatible
Maker	Toshiba Semiconductor
Parts packaging code	SOIC
package instruction	0.300 INCH, 1.27 MM PITCH, LEAD FREE, PLASTIC, SOP-16
Contacts	16
Reach Compliance Code	unknown
series	4000/14000/40000
JESD-30 code	R-PDSO-G16
length	10.3 mm
Load capacitance (CL)	50 pF
Logic integrated circuit type	J-K FLIP-FLOP
Maximum Frequency@Nom-Sup	3500000 Hz
MaximumI(ol)	0.00061 A
Number of digits	2
Number of functions	2
Number of terminals	16
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Output polarity	COMPLEMENTARY
Package body material	PLASTIC/EPOXY
encapsulated code	SOP
Encapsulate equivalent code	SOP16,.3
Package shape	RECTANGULAR
Package form	SMALL OUTLINE
method of packing	TUBE
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
power supply	5/15 V
propagation delay (tpd)	300 ns
Certification status	Not Qualified
Maximum seat height	1.9 mm
Maximum supply voltage (Vsup)	18 V
Minimum supply voltage (Vsup)	3 V
Nominal supply voltage (Vsup)	5 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal form	GULL WING
Terminal pitch	1.27 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED
Trigger type	POSITIVE EDGE
width	5.3 mm
minfmax	12 MHz
Base Number Matches	1

	TC4027BF	TC4027
Description	dual J-K master-slave flip flop	dual J-K master-slave flip flop

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