MC68HC908GR16
Data Sheet
M68HC08
Microcontrollers
MC68HC908GR16
Rev. 5.0
04/2007
freescale.com
MC68HC908GR16
Data Sheet
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The following revision history table summarizes changes contained in this document. For your
convenience, the page number designators have been linked to the appropriate location.
Revision History
Date
February,
2003
Revision
Level
N/A
Initial release
Reorganized to meet latest publication standards for M68HC08 Family
documentation
May,
2003
1.0
Chapter 16 Serial Peripheral Interface (SPI) Module — Removed all
references to DMAS
Figure 4-2. CGM External Connections — Figure updated for consistency
Table 4-4. Example Filter Component Values — Table updated to reflect new
resistor values
Description
Page
Number(s)
N/A
N/A
193
65
76
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This product incorporates SuperFlash® technology licensed from SST.
© Freescale Semiconductor, Inc., 2004, 2007. All rights reserved.
MC68HC908GR16 Data Sheet, Rev. 5.0
Freescale Semiconductor
3
Revision History
Revision History (Continued)
Date
Revision
Level
Description
Figure 1-1. MCU Block Diagram — Removed data bus switch module
Figure 2-2. Control, Status, and Data Registers and Figure 5-1. Configuration
Register 2 (CONFIG2) — Changed name of bit 0 from SCIBDSRC to
ESCIBDSRC
14.8.8 ESCI Prescaler Register — Updated description in this subsection
September,
2004
14.9.1 ESCI Arbiter Control Register — Updated description of ACLK bit
2.0
14.9.3 Bit Time Measurement — Updated bit time measurement mode for
ACLK = 0
Added dc injection current values to:
20.5 5.0-Vdc Electrical Characteristics
20.6 3.3-Vdc Electrical Characteristics
20.9.1 CGM Component Specifications — Corrected series resistor values
20.15 Memory Characteristics — Table updated to reflect new values
March,
2005
10.5 Clock Generator Module (CGM) — Updated description to remove
erroneous information.
20.9 Clock Generation Module Characteristics — Updated to reflect correct
values.
Table 13-2. Interrupt Source Flags — Changed IF7 to TIM2 channel instead
of Reserved.
January,
2007
4.0
Table 2-1. Vector Addresses — Changed address $FFEE to TIM2 Channel 1
Vector (High) and $FFEF to TIM2 Channel 1 Vector (Low) from Reserved
Figure 2-2. Control, Status, and Data Registers — Changed addresses
$0033 to $0035 to show TIM2 Channel 1 registers.
Figure 2-2. Control, Status, and Data Registers
— Replaced TMCLKSEL with
TMBCLKSEL to be compatile with development tool nomenclature
Chapter 5 Configuration Register (CONFIG)
— Changed COPCLK to
CGMXCLK, replaced TMCLKSEL with TMBCLKSEL to be compatible with
development tool nomenclature, and replaced exponents for COP timeout
period
6.2 Functional Description
— Replaced exponents for COP timeout period
April,
2007
10.6.2 Stop Mode
— Changed COPCLK to CGMXCLK
5.o
Figure 14-2. ESCI Module Block Diagram
— Replaced BUS_CLK with BUS
CLOCK and removed reference to rx BUSCLK
Figure 14-5. ESCI Transmitter
and
Figure 14-6. ESCI Receiver Block
Diagram
— Added CGMXCLK OR to BUS CLOCK designator
14.8.7 ESCI Baud Rate Register
— Replaced description of the LINT and
LINR bits
Figure 17-1 . Timebase Block Diagram
and
17.5 TBM Interrupt Rate—
Replaced TBMCLKSEL with TMBCLKSEL to be compatible with
development tool nomenclature
Page
Number(s)
22
29
and
78
168
172
173
253
255
258
265
112
260
144
37
29
32
3.0
79
84
113
149
151
154
169
218
219
MC68HC908GR16 Data Sheet, Rev. 5.0
4
Freescale Semiconductor
List of Chapters
Chapter 1 General Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Chapter 2 Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Chapter 3 Analog-to-Digital Converter (ADC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Chapter 4 Clock Generator Module (CGM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Chapter 5 Configuration Register (CONFIG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Chapter 6 Computer Operating Properly (COP) Module . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Chapter 7 Central Processor Unit (CPU). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Chapter 8 External Interrupt (IRQ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Chapter 9 Keyboard Interrupt Module (KBI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Chapter 10 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Chapter 11 Low-Voltage Inhibit (LVI). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Chapter 12 Input/Output Ports (PORTS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
Chapter 13 Resets and Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .135
Chapter 14 Enhanced Serial Communications Interface (ESCI) Module . . . . . . . . . . . . . 147
Chapter 15 System Integration Module (SIM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
Chapter 16 Serial Peripheral Interface (SPI) Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
Chapter 17 Timebase Module (TBM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217
Chapter 18 Timer Interface Module (TIM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221
Chapter 19 Development Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237
Chapter 20 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253
Chapter 21 Ordering Information and Mechanical Specifications . . . . . . . . . . . . . . . . . . 269
MC68HC908GR16 Data Sheet, Rev. 5.0
Freescale Semiconductor
5
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