C3 : Tight tolerance, temp-compensated electrolytic type
(Note : The capacitance value depends on the PWM control
scheme used in the applied system).
C4 : 0.22~2µF R-category ceramic capacitor for noise filtering.
High-side input (PWM)
(5V line) (Note 1,2)
Input signal Input signal Input signal
coditioning coditioning coditioning
Level shifter Level shifter Level shifter
Protection
circuit (UV)
C4
C3
Protection
circuit (UV)
Protection
circuit (UV)
(Note 6)
DIP-IPM
Inrush current
limiter circuit
Drive circuit Drive circuit Drive circuit
P
H-side IGBT
S
AC input
(Note 4)
C
Z
U
V
W
M
AC line output
Fig. 3
N
1
V
NC
N
CIN
Drive circuit
L-side IGBT
S
Z : ZNR (Surge absorber)
C : AC filter (Ceramic capacitor 2.2~6.5nF)
(Note : Additionally, an appropriate line to line
surge absorber circuit may become necessary
depending on the application environment.)
Input signal conditioning
Fo logic
SC
protection
Control supply
Under-Voltage
protection
F
O
CFO
Low-side input (PWM)
(5V line)
(Note 1, 2) F
O
output (5V line)
(Note 3, 5)
Note1:
2:
3:
4:
5:
6:
To prevent the input signals oscillation, an RC coupling at each input is recommended. (see also Fig. 6)
By virtue of integrating an application specific type HVIC inside the module, direct coupling to CPU terminals without any opto-coupler or transformer
isolation is possible. (see also Fig. 6)
This output is open collector type. The signal line should be pulled up to the positive side of the 5V power supply with approximately 5.1kΩ resistance.
(see also Fig. 6)
The wiring between the power DC link capacitor and the P/N1 terminals should be as short as possible to protect the DIP-IPM against catastrophic high
surge voltages. For extra precaution, a small film type snubber capacitor (0.1~0.22µF, high voltage type) is recommended to be mounted close to
these P and N1 DC power input terminals.
Fo output pulse width should be decided by connecting external capacitor between CFO and V
NC
terminals. (Example : C
FO
=22nF
→
t
FO
=1.8ms (Typ.))
High voltage (600V or more) and fast recovery type (less than 100ns) diodes should be used in the bootstrap circuit.
V
NC
V
D
(15V line)
Fig. 3 EXTERNAL PART OF THE DIP-IPM PROTECTION CIRCUIT
DIP-IPM
Drive circuit
P
Short Circuit Protective Function (SC) :
SC protection is achieved by sensing the L-side DC-Bus current (through the external
shunt resistor) after allowing a suitable filtering time (defined by the RC circuit).
When the sensed shunt voltage exceeds the SC trip-level, all the L-side IGBTs are turned
OFF and a fault signal (Fo) is output. Since the SC fault may be repetitive, it is
recommended to stop the system when the Fo signal is received and check the fault.
I
C
(A)
SC Protection
Trip Level
H-side IGBT
S
U
V
W
L-side IGBT
S
External protection circuit
N1
Shunt Resistor
(Note 1)
A
N
V
NC
CIN
B
Drive circuit
Collector current
waveform
C R
C
Protection circuit
(Note 2)
0
2
t
w
(µs)
Note1:
In the recommended external protection circuit, please select the RC time constant in the range 1.5~2.0µs.
2:
To prevent erroneous protection operation, the wiring of A, B, C should be as short as possible.
Sep. 2001
MITSUBISHI SEMICONDUCTOR <Intelligent Power Module>
PS20351-N
TRANSFER-MOLD TYPE
INSULATED TYPE
MAXIMUM RATINGS
(T
j
= 25°C, unless otherwise noted)
INVERTER PART
Symbol
V
CC
V
CC(surge)
V
CES
±I
C
±I
CP
P
C
T
j
Parameter
Supply voltage
Supply voltage (surge)
Collector-emitter voltage
Each IGBT collector current
Each IGBT collector current (peak)
Collector dissipation
Junction temperature
Condition
Applied between P-N
Applied between P-N
T
f
= 25°C
T
f
= 25°C, instantaneous value (pulse)
T
f
= 25°C, per 1 chip
(Note 1)
Ratings
350
400
500
3
6
17.8
–20~+150
Unit
V
V
V
A
A
W
°C
Note 1
: The maximum junction temperature rating of the power chips integrated within the DIP-IPM is 150°C (@ T
f
≤
100°C). However, to
ensure safe operation of the DIP-IPM, the average junction temperature should be limited to T
j(ave)
≤
125°C (@ T
f
≤
100°C).
CONTROL (PROTECTION) PART
Symbol
V
D
V
DB
V
CIN
V
FO
I
FO
V
SC
Parameter
Control supply voltage
Control supply voltage
Input voltage
Fault output supply voltage
Fault output current
Current sensing input voltage
Condition
Applied between V
P1
-V
NC
, V
N1
-V
NC
Applied between V
UFB
-V
UFS
, V
VFB
-V
VFS
,
V
WFB
-V
WFS
Applied between U
P
, V
P
, W
P
-V
NC
,
U
N
, V
N
, W
N
-V
NC
Applied between F
O
-V
NC
Sink current at F
O
terminal
Applied between CIN-V
NC
Ratings
20
20
–0.5~V
D
+0.5
–0.5~V
D
+0.5
15
–0.5~V
D
+0.5
Unit
V
V
V
V
mA
V
TOTAL SYSTEM
Parameter
V
CC(PROT)
Self protection supply voltage limit
(short-circuit protection capability)
Heat-fin operation temperature
T
f
T
stg
Storage temperature
V
iso
Isolation voltage
Symbol
Condition
V
D
= V
DB
= 13.5~16.5V, Inverter part
T
j
= 125°C, non-repetitive, less than 2
µs
(Note 2)
60Hz, Sinusoidal, 1 minute, connection
pins to heat-sink plate
Ratings
330
–20~+100
–40~+125
1500
Unit
V
°C
°C
V
rms
Note 2 : T
f
MEASUREMENT POINT
Al Board Specifications:
Dimensions 100
×
100
×
10mm, finishing: 12s, warp: –50~100µm
C
ontrol Terminals
FWD Chip
18mm
16mm
Al Board
IGBT/FWD Chip
Groove
IGBT Chip
Temp. measurement
point
(inside the Al board)
N
W
V
U
P
Temp. measurement point
(inside the Al board)
Power Terminals
100~200µm of evenly applied Silicon-Grease
Sep. 2001
MITSUBISHI SEMICONDUCTOR <Intelligent Power Module>
PS20351-N
TRANSFER-MOLD TYPE
INSULATED TYPE
THERMAL RESISTANCE
Symbol
R
th(j-f)Q
R
th(j-f)F
Parameter
Junction-to-heat sink thermal
resistance
Condition
Inverter IGBT part (per 1/6 module)
Inverter FWD part (per 1/6 module)
(Note 3)
(Note 3)
Limits
Min.
—
—
Typ.
—
—
Max.
7.0
8.0
Unit
°C/W
°C/W
Note 3 :
Grease with good thermal conductivity should be applied evenly about +100µm~+200µm on the contact surface of a DIP-IPM and a
heat sink.
ELECTRICAL CHARACTERISTICS
(T
j
= 25°C, unless otherwise noted)
INVERTER PART
Symbol
V
CE(sat)
V
EC
t
on
t
rr
t
c(on)
t
off
t
c(off)
I
CES
Parameter
Collector-emitter saturation
voltage
FWD forward voltage
Condition
I
C
= 3A, T
j
= 25°C
V
D
= V
DB
= 15V
V
CIN
= 0V
I
C
= 3A, T
j
= 125°C
T
j
= 25°C, –I
C
= 5A, V
CIN
= 5V
V
CC
= 280V, V
D
= V
DB
=15V
I
C
= 3A, T
j
= 125°C
Switching times
Inductive load (upper-lower arm)
V
CIN
= 5
↔
0V
V
CE
= V
CES
T
j
= 25°C
T
j
= 125°C
Min.
—
—
—
0.4
—
—
—
—
—
—
Limits
Typ.
1.7
1.8
1.9
0.9
0.25
0.35
0.90
0.45
—
—
Max.
2.35
2.45
2.6
1.35
—
0.60
1.35
0.95
1
10
Unit
V
V
µs
µs
µs
µs
µs
mA
Collector-emitter cut-off
current
CONTROL (PROTECTION) PART
Symbol
Parameter
Condition
Total of V
P1
-V
NC
, V
N1
-V
NC
V
D
= V
DB
=15V
V
CIN
= 5V
V
UFB
-V
UFS
, V
VFB
-V
VFS
, V
WFB
-V
WFS
Total of V
P1
-V
NC
, V
N1
-V
NC
V
D
= V
DB
=15V
V
UFB
-V
UFS
, V
VFB
-V
VFS
, V
WFB
-V
WFS
V
CIN
= 0V
V
SC
= 0V, F
O
= 10kΩ 5V pull-up
V
SC
= 1V, I
FO
= 1.5mA
V
SC
= 1V, I
FO
= 15mA
(Note 4)
T
j
=
25°C, V
D
= 15V
Trip level
Reset level
T
j
≤
125°C
Trip level
Reset level
Min.
—
—
—
—
4.9
—
0.8
0.43
10.0
10.5
10.3
10.8
1.0
0.8
2.5
Limits
Typ.
—
—
—
—
—
0.6
1.2
0.48
—
—
—
—
1.8
1.4
3.0
Max.
8.5
1.0
9.7
1.0
—
0.9
1.8
0.53
12.0
12.5
12.5
13.0
—
2.0
4.0
Unit
mA
mA
V
V
V
V
V
V
V
V
ms
V
V
I
D
Circuit current
Fault output pulse width
(Note 5)
C
FO
= 22nF
Applied between:
ON threshold voltage
U
P
, V
P
, W
P
-V
NC
, U
N
, V
N
, W
N
-V
NC
OFF threshold voltage
Note 4 :
Short-circuit protection operates only at the low-arms. Please select the value of the external shunt resistor such that the SC trip level
is less than 5.1A
5 :
Fault signal is outputted when the low-arm short-circuit or control supply under-voltage protective functions operate. The fault output
pulse-width t
FO
depends on the capacitance value of C
FO
according to the following approximate equation. : C
FO
= (12.2
✕
10
-6
)
✕
t
FO
[F]
V
FOH
V
FOL
V
FOsat
V
SC(ref)
UV
DBt
UV
DBr
UV
Dt
UV
Dr
t
FO
V
th(on)
V
th(off)
Fault output voltage
Short-circuit trip level
Supply circuit under-voltage
protection
Sep. 2001
MITSUBISHI SEMICONDUCTOR <Intelligent Power Module>
京公网安备 11010802033920号
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