DISCRETE SEMICONDUCTORS
DATA SHEET
PMBFJ174 to 177
P-channel silicon field-effect
transistors
Product specification
File under Discrete Semiconductors, SC07
April 1995
Philips Semiconductors
Product specification
P-channel silicon field-effect transistors
DESCRIPTION
Silicon symmetrical p-channel
junction FETs in plastic
microminiature SOT23
envelopes.They are intended for
application with analogue switches,
choppers, commutators etc. using
SMD technology. A special feature is
the interchangeability of the drain and
source connections.
PINNING
1
2
PMBFJ174 to 177
handbook, halfpage
3
d
s
g
1 = drain
2 = source
3 = gate
Note
1. Drain and source are
interchangeable.
Marking codes:
174
175
176
177
: p6X
: p6W
: p6S
: p6Y
Fig.1 Simplified outline and symbol, SOT23.
Top view
MAM386
QUICK REFERENCE DATA
Drain-source voltage
Gate-source voltage
Gate current
Total power dissipation
up to T
amb
= 25
°C
Drain current
−V
DS
= 15 V; V
GS
= 0
Drain-source ON-resistance
−V
DS
= 0,1 V; V
GS
= 0
R
DS on
<
85
125
250
300
Ω
P
tot
−I
DSS
max.
PMBFJ174
>
<
20
135
7
70
300
175
176
2
35
177
1,5 mA
20 mA
mW
±
V
DS
V
GSO
−I
G
max.
max.
max.
30
30
50
V
V
mA
April 1995
2
Philips Semiconductors
Product specification
P-channel silicon field-effect transistors
RATINGS
Limiting values in accordance with the Absolute Maximum System (IEC 134)
Drain-source voltage
Gate-source voltage
Gate-drain voltage
Gate current (d.c.)
Total power dissipation
up to T
amb
= 25
°C
(1)
Storage temperature range
Junction temperature
THERMAL RESISTANCE
From junction to ambient in free air
STATIC CHARACTERISTICS
T
j
= 25
°C
unless otherwise specified
R
th j-a
=
P
tot
T
stg
T
j
max.
max.
±
V
DS
V
GSO
V
GDO
−I
G
max.
max.
max.
max.
PMBFJ174 to 177
30
30
30
50
300
−65
to
+
150
150
V
V
V
mA
mW
°C
°C
430
K/W
PMBFJ174
Gate cut-off current
V
GS
= 20 V; V
DS
= 0
Drain cut-off current
−V
DS
= 15 V; V
GS
= 10 V
Drain current
−V
DS
= 15 V; V
GS
= 0
Gate-source breakdown voltage
I
G
= 1
µA;
V
DS
= 0
Gate-source cut-off voltage
−I
D
= 10 nA; V
DS
=
−15
V
Drain-source ON-resistance
−V
DS
= 0,1 V; V
GS
= 0
Note
1. Mounted on a ceramic substrate of 8 mm
×
10 mm
×
0,7 mm.
R
DS on
<
85
V
GS off
V
(BR)GSS
>
>
<
30
5
10
−I
DSS
−I
DSX
<
>
<
1
20
135
I
GSS
<
1
175
1
1
7
70
176
1
1
2
35
177
1 nA
1 nA
1,5 mA
20 mA
30
3
6
30
30 V
1
0,8 V
4 2,25 V
125
250
300
Ω
April 1995
3
Philips Semiconductors
Product specification
P-channel silicon field-effect transistors
DYNAMIC CHARACTERISTICS
T
j
= 25
°C
unless otherwise specified
Input capacitance, f = 1 MHz
V
GS
= 10 V; V
DS
= 0 V
V
GS
= V
DS
= 0
Feedback capacitance, f = 1 MHz
V
GS
= 10 V; V
DS
= 0 V
Switching times (see Fig.2
+
3)
Delay time
Rise time
Turn-on time
Storage temperature
Fall time
Turn-off time
Test conditions:
t
d
t
r
t
on
t
s
t
f
t
off
−V
DD
V
GS off
R
L
V
GS on
C
rs
typ.
PMBFJ174
typ.
typ.
typ.
typ.
typ.
typ.
2
5
7
5
10
15
10
12
560
0
C
is
C
is
typ.
typ.
PMBFJ174 to 177
8
30
4
175
5
10
15
10
20
30
6
8
1200
0
176
15
20
35
15
20
35
6
6
2000
0
177
pF
pF
pF
20 ns
25 ns
45 ns
20 ns
25 ns
45 ns
6 V
3 V
2900
Ω
0 V
handbook, halfpage
−V
DD
50
Ω
Vout
RL
Vin
50
Ω
OUTPUT
D.U.T
INPUT
VGSoff
90%
10%
10%
10%
90%
tf
ts
MBK292
90%
tr
td
MBK293
Rise time input voltage
<
1 ns
Fig.2 Switching times test circuit
Fig.3 Input and output waveforms
t
d
+
t
r
= t
on
t
s
+
t
f
= t
off
April 1995
4
Philips Semiconductors
Product specification
P-channel silicon field-effect transistors
PACKAGE OUTLINE
Plastic surface mounted package; 3 leads
PMBFJ174 to 177
SOT23
D
B
E
A
X
HE
v
M
A
3
Q
A
A1
1
e1
e
bp
2
w
M
B
detail X
Lp
c
0
1
scale
2 mm
DIMENSIONS (mm are the original dimensions)
UNIT
mm
A
1.1
0.9
A
1
max.
0.1
b
p
0.48
0.38
c
0.15
0.09
D
3.0
2.8
E
1.4
1.2
e
1.9
e
1
0.95
H
E
2.5
2.1
L
p
0.45
0.15
Q
0.55
0.45
v
0.2
w
0.1
OUTLINE
VERSION
SOT23
REFERENCES
IEC
JEDEC
EIAJ
EUROPEAN
PROJECTION
ISSUE DATE
97-02-28
April 1995
5
京公网安备 11010802033920号
EEWORLD
