EEWORLDEEWORLDEEWORLD

Part Number

Search

PL580-68QC

Description
320-640MHz Low Phase Noise VCXO
CategoryPassive components    oscillator   
File Size277KB,10 Pages
ManufacturerPLL (PhaseLink Corporation)
Download Datasheet Parametric View All

PL580-68QC Overview

320-640MHz Low Phase Noise VCXO

PL580-68QC Parametric

Parameter NameAttribute value
MakerPLL (PhaseLink Corporation)
Reach Compliance Codeunknow
(Preliminary)
PL580-68/69
320-640MHz Low Phase Noise VCXO
FEATURES
Less than 0.4ps RMS (12KHz-20MHz) phase
jitter for
all frequencies
.
Low phase noise output (@ 1MHz frequency
offset
-140dBc/Hz for 320.0MHz,
-131dBC/Hz for 622.08MHz
20MHz-40MHz crystal input.
320MHz-640MHz output.
Available in PECL, or LVDS outputs.
No external varicap required.
Output Enable selector.
Wide pull range (+/-200ppm).
3.3V operation.
Available in 3x3 QFN or 16-pin TSSOP
packages.
PACKAGE PIN ASSIGNMENT
VDDANA
XIN
XOUT
SEL2^
OE_CTRL
VCON
GNDANA
LP
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
SEL0^
SEL1^
GNDBUF
QBAR
VDDBUF
Q
GNDBUF
LM
PL580-6X
VDDANA
DNC
10
DESCRIPTION
The PL580-6X is a monolithic low jitter and low
phase noise VCXO, capable of 0.4ps RMS phase
jitter and PECL or LVDS outputs, covering a wide
frequency output range up to 640MHz. It allows the
control of the output frequency with an input voltage
(VCON), using a low cost crystal.
The PL580-6X is designed to address the
demanding requirements of high performance
applications such as SONET, GPS, Video, etc.
XOUT
DNC
OE_CTRL
VCON
12
13
14
15
16
1
11
DNC
9
XIN
8
7
6
GNDBUF
QBAR
VDDBUF
Q
PL580-6X
2
3
4
5
GNDANA
Note1: ^ Denotes internal pull up resistor.
BLOCK DIAGRAM
VCON
VARICAP
VCO
Divider
Charge
Pump
+
Loop
Filter
GNDBUF
LP
LM
XIN
XOUT
XTAL
OSC
Phase
Detector
VCO
(F
XiN
x16)
Output
Divider
QBAR
Q
Performance Tuner
OE
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 11/28/05 Page 1
usbkey
Engaged in professional cos development work, familiar with the working principles of various cos, willing to explore the following work for a long time: 1. Develop various USB dongles, USBkey develop...
whimsy Embedded System
Working Principle of Digital TV Encoder and Its Video Image Compression Format
This article briefly introduces what a digital TV encoder is , and analyzes its working principle, performance and characteristics in detail. It also introduces how to compress video images and what f...
sairvee Mobile and portable
Basic questions about capacitors
Recently I read the post of moderator RCD, which discussed many issues about MOS Coss and benefited a lot. RCD calculation method https://bbs.eeworld.com.cn/thread-1087737-1-1.html I happened to read ...
不亦心 Power technology
How to design a multi-uart port communication module?
I think after realizing one channel of UART communication, I can define another top-level entity, and call the following UART module multiple times in this entity! [In Chapter 5 of "FPGA Design Exampl...
qinyonglyz FPGA/CPLD
Learn Python the Hard Way (Third Edition)
Learn Python The Hard Way (LPTHW) is an introductory book on Python written by Zed Shaw. It is suitable for people who don't know much about computers and have never learned programming, but are inter...
arui1999 Download Centre
Application of FPGA in Software Radio
[b]Abstract[/b]: This article introduces the application of Rohde & Schwarz's handheld spectrum analyzer R&S FSH in transmitter and antenna test, radio interference investigation and electromagnetic c...
alexa FPGA/CPLD

EEWorld
subscription
account

EEWorld
service
account

Automotive
development
circle

Robot
development
community

Index Files: 865  2247  441  2457  1523  18  46  9  50  31 
Datasheet   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Room 1530, 15th Floor, Building B, No. 18 Zhongguancun Street, Haidian District, Beijing Telephone: (010) 82350740 Postal Code: 100190
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved 京ICP证060456号 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号