Application of FPGA in Software Radio

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Application of FPGA in Software Radio [Copy link]

Abstract: This article introduces the application of Rohde & Schwarz's handheld spectrum analyzer R&S FSH in transmitter and antenna test, radio interference investigation and electromagnetic compatibility diagnostic test in combination with various practical tests. Keywords: Transmitter and antenna test; Radio interference location; Electromagnetic field strength monitoring; Electromagnetic compatibility (EMC) diagnostic test

Introduction --- Software defined radio (SDR) is a wireless device with a reconfigurable hardware platform that can span multiple communication standards. Because of its lower cost, greater flexibility and higher performance, software defined radio has quickly become the de facto standard in the military, public safety and commercial wireless fields. One of the main reasons why SDR has become popular in commercial applications is its ability to perform baseband processing and digital intermediate frequency (IF) processing on a variety of waveforms. IF processing extends the scope of digital signal processing from baseband to RF. The ability to support baseband and IF processing increases system flexibility while reducing manufacturing costs. Baseband Processing --- Wireless standards continue to evolve, supporting higher data rates through advanced baseband processing techniques such as adaptive modulation and coding, space-time coding (STC), beamforming, and multiple-input multiple-output (MIMO) antenna technology. Baseband signal processing devices require huge processing bandwidth to support the computationally intensive algorithms in these techniques. For example, the U.S. military Joint Tactical Radio System (JTRS) defines more than 20 different radio waveforms for military wireless. The computational power required for some of the more complex waveforms is in the millions of instructions per second (MIPS) on a standard processor and thousands of logic cells if implemented on an FPGA. Coprocessor Features --- SDR baseband processing typically requires a processor and an FPGA. In such applications, the processor handles system control and configuration functions, while the FPGA implements the computationally intensive signal processing data path and control to minimize system latency. When it is necessary to switch from one standard to another, the processor can dynamically switch between the main parts of the software, while the FPGA can be completely reconfigured as needed to implement the data path for a specific standard. --- FPGAs can be connected to DSPs and general-purpose processors as coprocessors, which has higher system performance and lower system cost. The freedom to choose where to implement baseband processing algorithms provides another flexibility for implementing SDR algorithms. --- The baseband component also needs to be flexible enough to allow the required SDR functions to support migration between enhanced versions of the same standard and to support completely different standards. Programmable logic combined with soft-core processors and IP has the ability to provide remote upgrades in the field. Figure 1 is a block diagram in which an FPGA can be easily reconfigured to support baseband transmit functions for WCDMA/HSPDA or 802.16a standards through IP functions such as turbo encoders, Reed-Solomon encoders, symbol interleavers, symbol mappers, and IFFT. Digital IF Processing --- Digital frequency changes have higher performance than traditional analog radio processing methods. FPGAs provide a highly flexible and integrated platform on which to implement computationally intensive digital IF functions at reasonable power, a critical factor in portable systems. IF functions that can be implemented on FPGAs include digital upconverters (DUCs) and downconverters (DDCs), as well as digital predistortion (DPD) and crest factor reduction (CFR), helping to reduce the cost and power of power amplifiers (see Figure 2). --- Notes: DUC: digital upconverter; CFR: crest factor reduction; DPD: digital predistortion; DDC: digital downconverter; PA: power amplifier; LNA: low noise amplifier. Digital Upconverters --- Digital formats (generally required between the baseband processing unit and the upconverter) can be smoothly added to the front end of the upconverter. This technology provides a fully customized front end for the upconverter, allowing channelization of high-bandwidth input data. Custom logic or a soft-core embedded processor can be used to control the interface between the upconverter and the baseband processing unit implemented in the FPGA. --- In digital upconversion, the input data is baseband filtered and interpolated before being quadrature modulated with an adjustable carrier frequency. To implement the interpolated baseband finite impulse response (FIR) filters, a speed-area trade-off must be made to obtain a fixed or adaptive architecture optimized for a particular standard. The digitally controlled oscillator core can also produce a variety of architectures that have more than 115db spurious-free dynamic range and very high performance. Depending on the number of frequency allocations supported, multiple upconverters can be easily instantiated in the FPGA. Crest Factor Reduction --- 3G CDMA-based systems and multi-carrier systems such as orthogonal frequency division multiplexing (OFDM) have signals with a high peak-to-average ratio (crest factor). Such signals can significantly reduce the efficiency of the power amplifiers in base stations. For multiple waveform standards, crest factor reduction techniques implemented in FPGAs are a cost-effective way to reduce the cost and complexity of PAs. Digital Predistortion --- High-speed mobile data transmission uses non-constant envelope modulation techniques such as QPSK and quadrature amplitude modulation (QAM). This places stringent requirements on the linearity of the PA. DPD linearization techniques, including lookup tables and polynomial approaches, can be efficiently implemented in FPGAs containing DSP blocks. The multipliers in these DSP blocks can run at very high clock rates, which can effectively time-share the complex multiplication. When FPGAs are used in SDR base stations, the FPGAs can be reconfigured to implement the appropriate DPD algorithm for a specific standard, effectively linearizing the PA. Digital Downconverter --- On the receiver side, digital IF techniques can sample the IF signal and perform channelization and sample rate conversion in the digital domain. Using downsampling techniques, high-frequency IF signals (above 100 MHz at a time) can be quantized. Because different standards have different chip/bit rates, non-integer sampling rates are required for SDR applications, converting the number of samples to integer multiples of the basic chip/bit rate of any standard. Conclusion --- FPGA provides a general computing structure that is very suitable for the baseband and IF digital processing needs in software radio. In addition, FPGA, as a hardware coprocessor for general processors or DSP software processing, can enhance functionality, improve throughput, reduce system cost and lower system power.

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