MC74HC273 datasheet, PDF - EEWORLD Datasheet

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MC74HC273: DescriptionHC/UH SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PDIP20; Categorysemiconductor logic; File Size102KB，8 Pages; ManufacturerON Semiconductor; Websitehttp://www.onsemi.cn

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MC74HC273 Overview

HC/UH SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PDIP20

MC74HC273 Parametric

Parameter Name	Attribute value
Number of functions	1
Number of terminals	20
Maximum operating temperature	125 Cel
Minimum operating temperature	-55 Cel
Maximum supply/operating voltage	6 V
Minimum supply/operating voltage	2 V
Rated supply voltage	3 V
Processing package description	PLASTIC, DIP-20
state	ACTIVE
Craftsmanship	CMOS
packaging shape	RECTANGULAR
Package Size	IN-LINE
Terminal form	THROUGH-HOLE
Terminal spacing	2.54 mm
terminal coating	TIN LEAD
Terminal location	DUAL
Packaging Materials	PLASTIC/EPOXY
Temperature level	MILITARY
series	HC/UH
Logic IC type	D FLIP-FLOP
Number of digits	8
Output polarity	TRUE
propagation delay TPD	220 ns
Trigger type	POSITIVE EDGE
Max-Min frequency	24 MHz

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MC74HC273A

Octal D Flip-Flop with

Common Clock and Reset

High–Performance Silicon–Gate CMOS

The MC74HC273A is identical in pinout to the LS273. The device

inputs are compatible with standard CMOS outputs; with pullup

resistors, they are compatible with LSTTL outputs.

This device consists of eight D flip–flops with common Clock and

Reset inputs. Each flip–flop is loaded with a low–to–high transition of

the Clock input. Reset is asynchronous and active low.

http://onsemi.com

MARKING

DIAGRAMS

PDIP–20

N SUFFIX

CASE 738

•

Output Drive Capability: 10 LSTTL Loads

Outputs Directly Interface to CMOS, NMOS and TTL

Operating Voltage Range: 2.0 to 6.0 V

Low Input Current: 1.0

µA

High Noise Immunity Characteristic of CMOS Devices

In Compliance with the Requirements Defined by JEDEC Standard

No. 7A

•

Chip Complexity: 264 FETs or 66 Equivalent Gates

LOGIC DIAGRAM

DATA

INPUTS

CLOCK

NONINVERTING

OUTPUTS

MC74HC273AN

AWLYYWW

SOIC WIDE–20

DW SUFFIX

CASE 751D

TSSOP–20

DT SUFFIX

CASE 948E

HC273A

AWLYYWW

273A

ALYW

= Assembly Location

= Wafer Lot

= Year

= Work Week

PIN ASSIGNMENT

RESET

VCC

CLOCK

RESET

PIN 20 = VCC

PIN 10 = GND

FUNCTION TABLE

Inputs

Reset

Clock

Output

No Change

Value

Units

GND

Semiconductor Components Industries, LLC, 2000

May, 2000 – Rev. 9

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Design Criteria

Internal Gate Count*

Internal Gate Propagation Delay

Internal Gate Power Dissipation

Speed Power Product

1.5

5.0

µW

.0075

*Equivalent to a two–input NAND gate.

ORDERING INFORMATION

Device

MC74HC273AN

MC74HC273ADW

MC74HC273ADWR2

MC74HC273ADT

MC74HC273ADTR2

Package

PDIP–20

SOIC–WIDE

TSSOP–20

Shipping

1440 / Box

38 / Rail

1000 / Reel

75 / Rail

2500 / Reel

Publication Order Number:

MC74HC273A/D

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