Input High Voltage . . . . . . . . . . . . . . . . . . . . . . . (0.8 x V
DD
) to V
DD
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1.
θ
JA
is measured with the component mounted on an evaluation PC board in free air.
DC Electrical Specifications, 5.0V
PARAMETER
Output Voltage
All Outputs
SFTLOCK0, SFTLOCK1
Output High Voltage
LEDA0, LEDG0, LEDA1, LEDG1
SFTLOCK0, SFTLOCK1
V
DD
= 5.0V
±10%,
T
A
= 0
o
C to 85
o
C
SYMBOL
V
OL
V
OH
V
OH
V
OH
V
OL
V
OL
V
GOH
I
LOAD
= -16.0mA
I
LOAD
= -0.7mA
I
LOAD
= 1.6mA
I
LOAD
= 60µA
I
LOAD
< 10µA
CONDITIONS
-10µA < I
LOAD
< 10µA
-
V
DD
- 0.1
V
LED
- 1.0
V
DD
- 0.3
-
-
V
GATE
-0.5V
-15
0.7•V
DD
0.7•V
DD
0.7•V
DD
V
SS
-
-
-
-
-
-
V
GATE
-0.3V
-35
-
-
-
-
0.1
-
-
-
0.4
0.4
V
GATE
V
V
V
V
V
V
V
MIN
TYP
MAX
UNITS
Output Low Voltage
SCK, SDA, ALRT, SFTLOCK0, SFTLOCK1,
LEDG0, LEDA0, LEDG1, LEDA1
PWREN0, PWREN1
Gate Output High Voltage
PWREN0, PWREN1
Gate Output Current Source
PWREN0, PWREN1
Input High Voltage
1394PR0, USBPR0, REMREQ0, SECURE0,
1394PR1, USBPR1, REMREQ1, SECURE1
SCK, SDA
RESET, CLK
Input Low Voltage
1394PR0, USBPR0, REMREQ0, SECURE0,
1394PR1, USBPR1, REMREQ1, SECURE1,
RESET, CLK
SCK, SDA
Input/Output Leakage Current:
RESET, CLK, AD0, AD1, SCK, SDA, ALRT
Input Pullup Current
1394PR0, USBPR0, REMREQ0, SECURE0,
1394PR1, USBPR1, REMREQ1, SECURE1
Input Hysteresis Voltage
SCK, SDA
CLK
RESET
I
GATE
V
IH
V
IH
V
IH
V
IL
-50
V
DD
V
DD
V
DD
0.2•V
DD
µA
V
V
V
V
V
IL
I
IOL
I
IN
V
SS
-
50
-
-
200
0.2•V
DD
±10
400
V
µA
µA
V
HYS
V
HYS
V
HYS
0.02
0.6
0.8
0.10
1.0
1.1
0.40
1.3
1.4
V
V
V
2-420
CDP1020
DC Electrical Specifications, 5.0V
PARAMETER
Capacitance
Supply Current (RUN)
V
DD
= 5.0V
±10%,
T
A
= 0
o
C to 85
o
C
(Continued)
SYMBOL
C
OUT
C
IN
I
DD
f
CLK
= 4.0MHz External
CONDITIONS
MIN
-
-
-
TYP
-
-
1.3
MAX
12
8
5.0
UNITS
pF
pF
mA
DC Electrical Specifications, 3.3V
PARAMETER
Output Voltage
All Outputs
SFTLOCK0, SFTLOCK1
Output High Voltage
LEDA0, LEDG0, LEDA1, LEDG1
SFTLOCK0, SFTLOCK1
Output Low Voltage
V
DD
= 3.3V
±10%,
T
A
= 0
o
C to 85
o
C
SYMBOL
CONDITIONS
-10µA < I
LOAD
< 10µA
V
OL
V
OH
V
OH
V
OH
V
OL
V
OL
V
GOH
I
LOAD
= -6.0mA
I
LOAD
= -0.4mA
I
LOAD
= 1.6mA
I
LOAD
= 50µA
I
LOAD
< 10µA
-
V
DD
- 0.1
V
LED
- 1.0
V
DD
- 0.3
-
-
-
-
0.1
-
V
V
MIN
TYP
MAX
UNITS
-
-
-
-
V
V
SCK, SDA, ALRT, SFTLOCK0, SFTLOCK1,
LEDG0, LEDA0, LEDG1, LEDA1
PWREN0, PWREN1
Gate Output High Voltage
PWREN0, PWREN1
Gate Output Current Source
PWREN0, PWREN1
Input High Voltage
1394PR0, USBPR0, REMREQ0, SECURE0,
1394PR1, USBPR1, REMREQ1, SECURE1
SCK, SDA
RESET, CLK
Input Low Voltage
1394PR0, USBPR0, REMREQ0, SECURE0,
1394PR1, USBPR1, REMREQ1, SECURE1,
RESET, CLK
SCK, SDA
Input/Output Leakage Current:
RESET, CLK, AD0, AD1, SCK, SDA, ALRT
Input Pullup Current
1394PR0, USBPR0, REMREQ0, SECURE0,
1394PR1, USBPR1, REMREQ1, SECURE1
Input Hysteresis Voltage
SCK, SDA
CLK
RESET
Capacitance
-
-
0.4
0.4
V
V
V
GATE
-0.5V
V
GATE
-0.3V
V
GATE
V
I
GATE
V
IH
V
IH
V
IH
V
IL
-10
-20
-30
µA
0.7•V
DD
0.7•V
DD
0.7•V
DD
V
SS
-
-
-
V
DD
V
DD
V
DD
0.2•V
DD
V
V
V
-
V
V
IL
I
IOL
I
IN
V
SS
-
-
0.2•V
DD
±10
V
µA
µA
-
20
80
160
V
HYS
V
HYS
V
HYS
C
OUT
C
IN
0.05
0.4
0.3
-
-
-
0.15
0.8
0.5
-
-
0.9
0.45
1.1
0.8
12
8
4.5
V
V
V
pF
pF
mA
Supply Current (RUN)
I
DD
2-421
CDP1020
t
LOW
SCK
t
HD:STA
t
HIGH
t
HD:STA
t
HD:DAT
t
SU:DAT
t
SU:STA
t
SU:STO
SDA
t
BUF
STOP
START
STOP
START
FIGURE 1. CONTROL TIMING
Control Timing
V
DD
= 3.3V
±10%,
T
A
= 0
o
C to 85
o
C
PARAMETER
SYMBOL
f
CLK
t
RSUS
t
RL
t
DB
f
SMB
t
BUF
t
HD:STA
t
SU:STA
t
SU:STO
t
HD:DAT
t
SU:DAT
t
TIMEOUT
t
LOW
t
HIGH
t
LOW:SEXT
t
LOW:MEXT
t
F
t
R
MIN
2.0
0.9
6
50
MAX
4.5
1
-
-
UNITS
MHz
ms
t
OSC
ms
Frequency Of Operation (4.0MHz nominal) (CLK Pin)
Suspend Recovery Start-up Time
RESET
Pulse Width (RESET Pin)
Input Debounce Time (1394PRx, USBPRx, REMREQx, SECUREx Pins)
SMBus
SCK and SDA Pins
SCK Frequency
SMBus Free Time
Hold Time After (Repeated) Start Condition
Repeated Start Condition Setup Time
Stop Condition Setup Time
Data Hold Time
Data Setup Time
SCK Time-out Period
SCK Low Period
SCK High Period
Slave SCK Extend Period (cumulative)
Master SCK Extend Period (cumulative)
SCK/SMBDAT Fall Time
SCK/SMBDAT Rise Time
10
4.7
4.0
4.7
4.0
300
250
25
4.7
4.0
-
-
-
-
100
-
-
-
-
-
-
35
-
50
25
10
300
1000
kHz
µs
µs
µs
µs
ns
ns
ms
µs
µs
ms
ms
ns
ns
Notational Conventions
The following conventions are used throughout this
document:
• Hexadecimal numbers are denoted with a “$” symbol
preceding the number.
• Binary numbers are represented with a “%” symbol
proceeding the number, or a “b” following.
• Because of the large mix of active-low and active-high
signals used in connection with the CDP1020, the terms
“asserted” and “de-asserted” will be used exclusively. An
active low signal is asserted when it is at a logic 0 and de-
asserted when it is at a logic 1 state. Conversely, an active
high signal is at a logic 1 state when asserted and at a
logic 0 state when de-asserted. The terms reset, clear,
and “low” can also mean logic 0; set or “high” can also
mean logic 1.
• Active low signals are represented with an overline; active
high signals have no overline. For example, REMREQ0 is
active low, PWREN0 is active high.
• There are many pins, signals, registers, and software bits
common to both Bay 0 and Bay 1; these names may
include the Bay number suffix (0 or 1), an “x” to represent
either, or no suffix at all. For example, PWREN, PWREN0,
or PWRENx may each be used to describe output pin(s).
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Embedded System
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