935262540112 datasheet, PDF - EEWORLD Datasheet

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935262540112: DescriptionLVC/LCX/Z SERIES, 9-BIT DRIVER, TRUE OUTPUT, PDSO24, 5.30 MM, PLASTIC, MO-150, SOT-340, SSOP-24; Categorylogic logic; File Size148KB，21 Pages; ManufacturerNXP; Websitehttps://www.nxp.com

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935262540112 Overview

LVC/LCX/Z SERIES, 9-BIT DRIVER, TRUE OUTPUT, PDSO24, 5.30 MM, PLASTIC, MO-150, SOT-340, SSOP-24

935262540112 Parametric

Parameter Name	Attribute value
Objectid	8074804537
package instruction	SSOP,
Reach Compliance Code	unknown
Other features	WITH CLEAR AND CLOCK ENABLE
series	LVC/LCX/Z
JESD-30 code	R-PDSO-G24
JESD-609 code	e4
length	8.2 mm
Logic integrated circuit type	BUS DRIVER
Number of digits	9
Number of functions	1
Number of ports	2
Number of terminals	24
Maximum operating temperature	125 °C
Minimum operating temperature	-40 °C
Output characteristics	3-STATE
Output polarity	TRUE
Package body material	PLASTIC/EPOXY
encapsulated code	SSOP
Package shape	RECTANGULAR
Package form	SMALL OUTLINE, SHRINK PITCH
propagation delay (tpd)	11.5 ns
Maximum seat height	2 mm
Maximum supply voltage (Vsup)	3.6 V
Minimum supply voltage (Vsup)	1.2 V
Nominal supply voltage (Vsup)	2.7 V
surface mount	YES
technology	CMOS
Temperature level	AUTOMOTIVE
Terminal surface	NICKEL PALLADIUM GOLD
Terminal form	GULL WING
Terminal pitch	0.65 mm
Terminal location	DUAL
width	5.3 mm

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74LVC823A

9-bit D-type flip-flop with 5 V tolerant inputs/outputs; positive

edge-trigger; 3-state

Rev. 4 — 8 April 2013

Product data sheet

1. General description

The 74LVC823A is a 9-bit D-type flip-flop with common clock (pin CP), clock enable

(pin CE), master reset (pin MR) and 3-state outputs (pins Qn) for bus-oriented

applications. The 9 flip-flops stores the state of their individual D-inputs that meet the

set-up and hold times requirements on the LOW to HIGH CP transition, provided pin CE is

LOW. When pin CE is HIGH, the flip-flops hold their data. A LOW on pin MR resets all

flip-flops. When pin OE is LOW, the contents of the 9 flip-flops are available at the outputs.

When pin OE is HIGH, the outputs go to the high-impedance OFF-state. Operation of the

OE input does not affect the state of the flip-flops.

Inputs can be driven from either 3.3 V or 5 V devices. When disabled, up to 5.5 V can be

applied to the outputs. These features allow the use of these devices as translators in

mixed 3.3 V and 5 V applications.

2. Features and benefits



5 V tolerant inputs/outputs for interfacing with 5 V logic

Wide supply voltage range from 1.2 V to 3.6 V

CMOS low power consumption

Direct interface with TTL levels

Flow-through pinout architecture

9-bit positive edge-triggered register

Independent register and 3-state buffer operation

Complies with JEDEC standard:



JESD8-7A (1.65 V to 1.95 V)



JESD8-5A (2.3 V to 2.7 V)



JESD8-C/JESD36 (2.7 V to 3.6 V)



ESD protection:



HBM JESD22-A114F exceeds 2000 V



MM JESD22-A115-B exceeds 200 V



CDM JESD22-C101E exceeds 1000 V



Specified from

40 C

to +85

C

and

40 C

to +125

C.

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