512Mb B-die DDR2 SDRAM
DDR2 SDRAM
512Mb B-die DDR2 SDRAM Specification
Version 1.5
July 2005
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AND IS SUBJECT TO CHANGE WITHOUT NOTICE.
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INFORMATION IN THIS DOCUMENT IS PROVIDED
ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND.
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* Samsung Electronics reserves the right to change products or specification without notice.
Page 1 of 28
Rev. 1.5 July 2005
512Mb B-die DDR2 SDRAM
0. Ordering Information
Organization
128Mx4
64Mx8
32Mx16
DDR2-533 4-4-4
K4T51043QB-GCD5
K4T51043QB-ZCD5
K4T51083QB-GCD5
K4T51083QB-ZCD5
K4T51163QB-GCD5
K4T51163QB-ZCD5
DDR2-400 3-3-3
K4T51043QB-GCCC
K4T51043QB-ZCCC
K4T51083QB-GCCC
K4T51083QB-ZCCC
K4T51163QB-GCCC
K4T51163QB-ZCCC
DDR2 SDRAM
Package
60 FBGA
60 FBGA
60 FBGA
60 FBGA
84 FBGA
84 FBGA
Note : Speed bin is in order of CL-tRCD-tRP.
1.Key Features
Speed
CAS Latency
tRCD(min)
tRP(min)
tRC(min)
DDR2-533 4-4-4
4
15
15
55
DDR2-400 3-3-3
3
15
15
55
Units
tCK
ns
ns
ns
• JEDEC standard 1.8V ± 0.1V Power Supply
• VDDQ = 1.8V ± 0.1V
• 200 MHz f
CK
for 400Mb/sec/pin, 267MHz f
CK
for 533Mb/sec/
pin
• 4 Banks
• Posted CAS
• Programmable CAS Latency: 3, 4, 5
• Programmable Additive Latency: 0, 1 , 2 , 3 and 4
• Write Latency(WL) = Read Latency(RL) -1
• Burst Length: 4 , 8(Interleave/nibble sequential)
• Programmable Sequential / Interleave Burst Mode
• Bi-directional Differential Data-Strobe (Single-ended data-
strobe is an optional feature)
• Off-Chip Driver(OCD) Impedance Adjustment
• On Die Termination
• Special Function Support
-High Temperature Self-Refresh rate enable
• Average Refresh Period 7.8us at lower than T
CASE
85°C,
3.9us at 85°C < T
CASE
< 95
°C
• Package: 60ball FBGA - 128Mx4/64Mx8 , 84ball FBGA -
32Mx16
• All of Lead-free products are compliant for RoHS
The 512Mb DDR2 SDRAM is organized as a 32Mbit x 4 I/Os x 4
banks, 16Mbit x 8 I/Os x 4banks or 8Mbit x 16 I/Os x 4 banks
device. This synchronous device achieves high speed double-
data-rate transfer rates of up to 533Mb/sec/pin (DDR2-533) for
general applications.
The chip is designed to comply with the following key DDR2
SDRAM features such as posted CAS with additive latency, write
latency = read latency -1, Off-Chip Driver(OCD) impedance
adjustment and On Die Termination.
All of the control and address inputs are synchronized with a pair
of externally supplied differential clocks. Inputs are latched at the
crosspoint of differential clocks (CK rising and CK falling). All I/Os
are synchronized with a pair of bidirectional strobes (DQS and
DQS) in a source synchronous fashion. The address bus is used
to convey row, column, and bank address information in a RAS/
CAS multiplexing style. For example, 512Mb(x4) device receive
14/11/2 addressing.
The 512Mb DDR2 device operates with a single 1.8V ± 0.1V
power supply and 1.8V ± 0.1V VDDQ.
The 512Mb DDR2 device is available in 60ball FBGAs(x4/x8) and
in 84ball FBGAs(x16).
Note: The functionality described and the timing specifications
included in this data sheet are for the DLL Enabled mode of oper-
ation.
Note : This data sheet is an abstract of full DDR2 specification and does not cover the common features which are described in “Samsung’s DDR2
SDRAM Device Operation & Timing Diagram”
Page 3 of 28
Rev. 1.5 July 2005
512Mb B-die DDR2 SDRAM
DDR2 SDRAM
x8 package pinout (Top View) : 60ball FBGA Package
1
2
NU/
RDQS
VSSQ
DQ1
VSSQ
VREF
CKE
NC
BA0
A10
VSS
A3
A7
VDD
A12
3
7
8
9
VDD
DQ6
VDDQ
DQ4
VDDL
VSS
DM/
RDQS
VDDQ
DQ3
VSS
WE
BA1
A1
A5
A9
NC
A
B
C
D
E
F
G
H
J
K
L
VSSQ
DQS
VDDQ
DQ2
VSSDL
RAS
CAS
A2
A6
A11
NC
DQS
VSSQ
DQ0
VSSQ
CK
CK
CS
A0
A4
A8
A13
VDDQ
DQ7
VDDQ
DQ5
VDD
ODT
VDD
VSS
Notes:
1. Pins B3 and A2 have identical capacitance as pins B7 and A8.
2. For a read, when enabled, strobe pair RDQS & RDQS are identical in function and timing to strobe pair DQS
& DQS and input masking function is disabled.
3. The function of DM or RDQS/RDQS are enabled by EMRS command.
4. VDDL and VSSDL are power and ground for the DLL.
Ball Locations (x8)
: Populated Ball
+ : Depopulated Ball
Top View
(See the balls through the Package)
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
G
H
J
K
L
+
+
+
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+
+
+
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+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
Page 5 of 28
Rev. 1.5 July 2005
FPGA/CPLD
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