Low Skew, 1-to18
LVPECL-to-LVCMOS/LVTTL Fanout Buffer
General Description
The ICS83940DI is a low skew, 1-to-18 LVPECL- to-LVCMOS/LVTTL
Fanout Buffer. The ICS83940DI has two selectable clock inputs. The
PCLK, nPCLK pair can accept LVPECL, CML, or SSTL input levels.
The LVCMOS_CLK can accept LVCMOS or LVTTL input levels. The
low impedance LVCMOS/LVTTL outputs are designed to drive 50Ω
series or parallel terminated transmission lines.
The ICS83940DI is characterized at full 3.3V and 2.5V or mixed 3.3V
core, 2.5V output operating supply modes. Guaranteed output and
part-to-part skew characteristics make the ICS83940DI ideal for
those clock distribution applications demanding well defined
performance and repeatability.
ICS83940DI
DATA SHEET
Features
•
•
•
•
•
•
•
•
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Eighteen LVCMOS/LVTTL outputs
Selectable LVCMOS_CLK or LVPECL clock inputs
PCLK, nPCLK pair can accept the following differential input
levels: LVPECL, CML, SSTL
LVCMOS_CLK supports the following input types: LVCMOS or
LVTTL
Maximum output frequency: 250MHz
Output skew: 150ps (maximum)
Part-to-part skew: 750ps (maximum)
Operating supply modes:
Core/Output
3.3V/3.3V
3.3V/2.5V
2.5V/2.5V
-40°C to 85°C ambient operating temperature
Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
Block Diagram
CLK_SEL
Pulldown
PCLK
Pulldown
nPCLK
Pullup/Pulldown
0
18
Q0:Q17
LVCMOS_CLK
Pulldown
1
Pin Assignments
V
DDO
V
DDO
GND
GND
Q4
Q0
Q1
Q2
Q3
Q4
Q5
Q3
Q0
Q2
Q5
Q1
32 31 30 29 28 27 26 25
GND
GND
LVCMOS_CLK
CLK_SEL
PCLK
nPCLK
V
DD
V
DDO
S
O
P
O
R
P
2
3
4
1
D
E
24
23
22
21
Q6
Q7
Q8
V
DD
20 Q9
19 Q10
18
17
Q11
GND
32 31 30 29 28 27 26 25
GND
GND
LVCMOS_CLK
CLK_SEL
PCLK
nPCLK
V
DD
V
DDO
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16
GND
V
DDO
Q17
Q16
Q15
Q14
Q13
Q12
24
23
Q6
Q7
Q8
V
DD
Q9
Q10
Q11
GND
ICS83940DI
ICS83940DI
22
21
20
19
18
17
5
6
7
8
9
10 11 12 13 14 15 16
GND
V
DDO
Q13
Q16
Q15
Q14
Q12
32 Lead VFQFN
5mm x 5mm x 0.925mm package body
K Package
Top View
ICS83940DYI REVISION C SEPTEMBER 7, 2010
1
Q17
32-Lead LQFP
7mm x 7mm x 1.4mm package body
Y Package
Top View
©2010 Integrated Device Technology, Inc.
ICS83940DI Data Sheet
LOW SKEW, 1-TO-18 LVPECL-TO-LVCMOS/LVTTL FANOUT BUFFER
Table 1. Pin Descriptions
Number
1, 2, 12, 17, 25
3
4
5
6
7, 21
8, 16, 29
9, 10, 11,
13, 14, 15,
18, 19, 20,
22, 23, 24,
26, 27, 28,
30, 31, 32
Name
GND
LVCMOS_CLK
CLK_SEL
PCLK
nPCLK
V
DD
V
DDO
Q17, Q16, Q15,
Q14, Q13, Q12,
Q11, Q10, Q9,
Q8, Q7, Q6,
Q5, Q4, Q3,
Q2, Q1, Q0
Power
Input
Input
Input
Input
Power
Power
Pulldown
Pulldown
Pulldown
Pullup/
Pulldown
Type
Description
Power supply ground.
Single-ended clock input. LVCMOS/LVTTL interface levels.
Clock select input. When HIGH, selects LVCMOS_CLK input.
When LOW, selects PCLK, nPCLK inputs.
LVCMOS / LVTTL interface levels.
Non-inverting differential LVPECL clock input.
Inverting differential LVPECL clock input. V
DD
/2 default when left floating.
Power supply pin.
Output supply pins.
Output
Single-ended clock outputs. LVCMOS/LVTTL interface levels.
NOTE:
Pullup and Pulldown
refers to internal input resistors. See Table 2,
Pin Characteristics,
for typical values.
Table 2. Pin Characteristics
Symbol
C
IN
R
PULLUP
R
PULLDOWN
C
PD
R
OUT
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Power Dissipation Capacitance
(per output)
Output Impedance
18
Test Conditions
Minimum
Typical
4
51
51
6
28
Maximum
Units
pF
k
Ω
k
Ω
pF
Ω
ICS83940DYI REVISION C SEPTEMBER 7, 2010
2
©2010 Integrated Device Technology, Inc.
ICS83940DI Data Sheet
LOW SKEW, 1-TO-18 LVPECL-TO-LVCMOS/LVTTL FANOUT BUFFER
Function Tables
Table 3A. Clock Select Function Table
Control Input
CLK_SEL
0
1
PCLK, nPCLK
Selected
De-selected
Clock
LVCMOS_CLK
De-selected
Selected
Table 3B. Clock Input Function Table
Inputs
CLK_SEL
0
0
0
0
0
0
1
1
LVCMOS_CLK
–
–
–
–
–
–
0
1
PCLK
0
1
0
1
Biased; NOTE 1
Biased; NOTE 1
–
–
nPCLK
1
0
Biased; NOTE 1
Biased; NOTE 1
0
1
–
–
Outputs
Q[0:17]
LOW
HIGH
LOW
HIGH
HIGH
LOW
LOW
HIGH
Input to Output Mode
Differential to Single-Ended
Differential to Single-Ended
Single-Ended to Single-Ended
Single-Ended to Single-Ended
Single-Ended to Single-Ended
Single-Ended to Single-Ended
Single-Ended to Single-Ended
Single-Ended to Single-Ended
Polarity
Non-Inverting
Non-Inverting
Non-Inverting
Non-Inverting
Inverting
Inverting
Non-Inverting
Non-Inverting
NOTE 1: Please refer to the Application Information Section,
Wiring the Differential Input to Accept Single-ended Levels.
ICS83940DYI REVISION C SEPTEMBER 7, 2010
3
©2010 Integrated Device Technology, Inc.
ICS83940DI Data Sheet
LOW SKEW, 1-TO-18 LVPECL-TO-LVCMOS/LVTTL FANOUT BUFFER
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under
Absolute Maximum Ratings
may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the
DC Characteristics or AC Characteristics
is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Item
Supply Voltage, V
DD
Inputs, V
I
Outputs, V
O
Input Current, I
IN
Storage Temperature, T
STG
Rating
3.6V
-0.3V to V
DD
+ 0.3V
-0.3V to V
DDO
+ 0.3V
±20mA
-65°C to 150°C
DC Electrical Characteristics
Table 4A. DC Characteristics,
V
DD
= V
DDO
= 3.3V ± 5%, T
A
= -40°C to 85°C
Symbol
V
IH
V
IL
I
IN
V
OH
V
OL
V
PP
V
CMR
I
DD
Parameter
Input High Voltage
Input Low Voltage
Input Current
Output High Voltage
Output Low Voltage
Peak-to-Peak Input Voltage;
NOTE 1
Common Mode Input Voltage;
NOTE 1, 2
Power Supply Current
PCLK, nPCLK
PCLK, nPCLK
I
OH
= -20mA
I
OL
= 20mA
500
V
DD
– 1.45
2.4
0.5
1000
V
DD
– 0.6
25
LVCMOS_CLK
LVCMOS_CLK
Test Conditions
Minimum
2.4
Typical
Maximum
V
DD
0.8
±200
Units
V
V
µA
V
V
mV
V
mA
NOTE 1: V
IL
should not be less than -0.3V.
NOTE 2: Common mode voltage is defined as V
IH
.
Table 4B. DC Characteristics,
V
DD
= 3.3V ± 5%, V
DDO
= 2.5V ± 5%, T
A
= -40°C to 85°C
Symbol
V
IH
V
IL
I
IN
V
OH
V
OL
V
PP
V
CMR
I
DD
Parameter
Input High Voltage
Input Low Voltage
Input Current
Output High Voltage
Output Low Voltage
Peak-to-Peak Input Voltage;
NOTE 1
Common Mode Input Voltage;
NOTE 1, 2
Power Supply Current
PCLK, nPCLK
PCLK, nPCLK
I
OH
= -20mA
I
OL
= 20mA
300
V
DD
– 1.4
1.8
0.5
1000
V
DD
– 0.6
25
LVCMOS_CLK
LVCMOS_CLK
Test Conditions
Minimum
2.4
Typical
Maximum
V
DD
0.8
±200
Units
V
V
µA
V
V
mV
V
mA
NOTE 1: V
IL
should not be less than -0.3V.
NOTE 2: Common mode voltage is defined as V
IH
.
ICS83940DYI REVISION C SEPTEMBER 7, 2010
4
©2010 Integrated Device Technology, Inc.
ICS83940DI Data Sheet
LOW SKEW, 1-TO-18 LVPECL-TO-LVCMOS/LVTTL FANOUT BUFFER
Table 4C. DC Characteristics,
V
DD
= V
DDO
= 2.5V ± 5%, T
A
= -40°C to 85°C
Symbol
V
IH
V
IL
I
IN
V
OH
V
OL
V
PP
V
CMR
I
DD
Parameter
Input High Voltage
Input Low Voltage
Input Current
Output High Voltage
Output Low Voltage
Peak-to-Peak Input Voltage;
NOTE 1
Common Mode Input Voltage;
NOTE 1, 2
Power Supply Current
PCLK, nPCLK
PCLK, nPCLK
I
OH
= -12mA
I
OL
= 12mA
300
V
DD
– 1.4
1.8
0.5
1000
V
DD
– 0.6
25
LVCMOS_CLK
LVCMOS_CLK
Test Conditions
Minimum
2
Typical
Maximum
V
DD
0.8
±200
Units
V
V
µA
V
V
mV
V
mA
NOTE 1: V
IL
should not be less than -0.3V.
NOTE 2: Common mode voltage is defined as V
IH
.
ICS83940DYI REVISION C SEPTEMBER 7, 2010
5
©2010 Integrated Device Technology, Inc.
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