C8051F346
USB, 25 MIPS, 64 kB Flash, 10-Bit ADC, 32-Pin Mixed-Signal MCU
Analog Peripherals
10-Bit ADC
High-Speed 8051 µC Core
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±1 LSB INL; no missing codes
Programmable throughput up to 200 ksps
Up to 17 external inputs; programmable as single-ended or differential
Built-in temperature sensor (±3 °C)
Pipelined instruction architecture; executes 70% of instructions in 1 or 2
system clocks
Up to 25 MIPS throughput with 25 MHz Clock
Expanded interrupt handler
4352 bytes data RAM (256 + 4 kB)
64 kB Flash; in-system programmable in 512-byte sectors (512 bytes
are reserved)
25 port I/O; all are 5 V tolerant
Hardware SMBus™ (I
2
C™ compatible), SPI™, and UART serial ports
available concurrently
4 general-purpose 16-bit counter/timers
Programmable 16-bit counter array with 5 capture/compare modules
Internal oscillator: 0.25% accuracy with clock recovery enabled;
supports all USB and UART modes
External oscillator: Crystal, RC, C, or Clock
On-chip clock multiplier: up to 48 MHz
On-chip voltage regulator supports USB bus-powered operation
Regulator bypass mode supports USB self-powered operation
Memory
Two Comparators
Internal Voltage Reference: 2.4 V
POR/Brown-out Detector
USB Function Controller
Digital Peripherals
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USB specification 2.0 compliant
Full-speed (12 Mbps) or low-speed (1.5 Mbps) operation
Integrated clock recovery; no external crystal required for either full-
speed or low-speed operation
Supports eight flexible endpoints
Dedicated 1 kB USB buffer memory
Integrated transceiver; no external resistors required
On-chip debug circuitry facilitates full speed, non-intrusive in-system
debug (no emulator required)
Provides breakpoints, single stepping
Inspect/modify memory, registers, and USB memory
Superior performance to emulation systems using ICE-chips, target
pods, and sockets
Clock Sources
On-Chip Debug
Voltage Regulator
Temperature Range: –40 to +85 °C
Operating Voltage: 2.7 to 5.25 V
Ordering Part Number
C8051F346-GQ, 32-Pin LQFP, 9x9 mm
2
C8051F346-GM, 32-Pin QFN, 5x5 mm
2
REGIN
5.0V
IN
Voltage
Regulator
OUT
Enable
Port 0
Latch
Port 1
Latch
Port 2
Latch
C
R
O
S
S
B
A
R
P
0
D
r
v
P
1
D
r
v
P
2
D
r
v
VDD
GND
Analog/Digital
Power
P0.0
P0.1
P0.2/XTAL1
P0.3/XTAL2
P0.4
P0.5
P0.6/CNVSTR
P0.7/VREF
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7
C2D
Debug HW
Reset
RST/C2CK
8
0
5
1
UART0
64 kB
FLASH
256 Byte
SRAM
4 kB
Timer
0,1,2,3 /
RTC
PCA/
WDT
SMBus
SPI
POR
XTAL1 XTAL2
Brown-
Out
External
Oscillator
Circuit
12 MHz
Internal
Oscillator
x4
÷2
System
Clock
XRAM
C
o
SFR Bus
r
e
Port 3
Latch
P
3
D
r
v
P3.0/C2D
VREF
÷2
Clock
Recovery
CP0
USB Clock
VREF
CP1
+
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+
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Temp
÷ 1,2,3,4
USB
Transceiver
USB
Controller
D+
D-
VDD
VBUS
1 kB USB
SRAM
10-bit
200 ksps
ADC
A
M
U
X
AIN0-AIN16
VDD
VREF
USB
Copyright © 2009 by Silicon Laboratories
4.8.2009
stm32/stm8
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