dsPIC30F
dsPIC30F Flash Programming Specification
1.0
OVERVIEW AND SCOPE
This document defines the programming specification
for the dsPIC30F family of Digital Signal Controllers
(DSCs). The programming specification is required
only for the developers of third-party tools that are used
to program dsPIC30F devices. Customers using
dsPIC30F devices should use development tools that
already provide support for device programming.
This document includes programming specifications
for the following devices:
•
•
•
•
•
•
dsPIC30F2010/2011/2012
dsPIC30F3010/3011/3012/3013/ 3014
dsPIC30F4011/4012/4013
dsPIC30F5011/5013/5015/5016
dsPIC30F6010/6011/6012/6013/6014/6015
dsPIC30F6010A/6011A/6012A/6013A/6014A
Two different methods are used to program the chip in
the user’s system. One method uses the Enhanced In-
Circuit Serial Programming™ (Enhanced ICSP™)
protocol and works with the programming executive.
The other method uses In-Circuit Serial Programming
(ICSP) protocol and does not use the programming
executive.
The Enhanced ICSP protocol uses the faster, high-
voltage method that takes advantage of the
programming executive. The programming executive
provides all the necessary functionality to erase,
program and verify the chip through a small command
set. The command set allows the programmer to
program the dsPIC30F without having to deal with the
low-level programming protocols of the chip.
The ICSP programming method does not use the
programming executive. It provides native, low-level
programming capability to erase, program and verify
the chip. This method is significantly slower because it
uses control codes to serially execute instructions on
the dsPIC30F device.
This specification describes the ICSP and Enhanced
ICSP
programming
methods.
Section 3.0
“Programming Executive Application”
describes
the
programming
executive
application
and
Section 5.0 “Device Programming”
describes its
application programmer’s interface for the host
Section 11.0
“ICSP™
Mode”
programmer.
describes the ICSP programming method.
2.0
PROGRAMMING OVERVIEW
OF THE dsPIC30F
The dsPIC30F family of DSCs contains a region of on-
chip memory used to simplify device programming.
This region of memory can store a programming
executive, which allows the dsPIC30F to be
programmed faster than the traditional means. Once
the programming executive is stored to memory by an
external programmer (such as Microchip’s MPLAB
®
ICD 2, MPLAB PM3, PRO MATE
®
II, or MPLAB REAL
ICE™), it can then interact with the external
programmer to efficiently program devices.
The programmer and programming executive have a
master-slave relationship, where the programmer is
the master programming device and the programming
executive is the slave, as illustrated in
Figure 2-1.
2.1
Hardware Requirements
FIGURE 2-1:
OVERVIEW OF dsPIC30F
PROGRAMMING
Programmer
2
Programming
Executive
On-chip Memory
dsPIC30F Device
In ICSP or Enhanced ICSP mode, the dsPIC30F
requires two programmable power supplies: one for
V
DD
and one for MCLR. For Bulk Erase programming,
which is required for erasing code protection bits, V
DD
must be greater than 4.5 volts. Refer to
Section 13.0
“AC/DC Characteristics and Timing Requirements”
for additional hardware parameters.
©
2010 Microchip Technology Inc.
DS70102K-page 1
dsPIC30F Flash Programming Specification
2.2
Pins Used During Programming
The pins identified in
Table 2-1
are used for device
programming. Refer to the appropriate device data
sheet for complete pin descriptions.
Locations 0x800000 through 0x8005BE are reserved
for executive code memory. This region stores either
the programming executive or debugging executive.
The programming executive is used for device
programming, while the debug executive is used for in-
circuit debugging. This region of memory cannot be
used to store user code.
Locations 0xF80000 through 0xF8000E are reserved
for the Configuration registers. The bits in these
registers may be set to select various device options,
and are described in
Section 5.7 “Configuration Bits
Programming”.
Locations 0xFF0000 and 0xFF0002 are reserved for
the Device ID registers. These bits can be used by the
programmer to identify what device type is being
programmed and are described in
Section 10.0
“Device ID”.
The device ID reads out normally, even
after code protection is applied.
Figure 2-2
illustrates the memory map for the
dsPIC30F devices.
TABLE 2-1:
Pin Name
MCLR/V
PP
V
DD
V
SS
PGC
PGD
dsPIC30F PIN DESCRIPTIONS
DURING PROGRAMMING
Pin Type
P
P
P
I
I/O
Pin Description
Programming Enable
Power Supply
Ground
Serial Clock
Serial Data
Legend:
I = Input, O = Output, P = Power
2.3
Program Memory Map
The program memory space extends from 0x0 to
0xFFFFFE. Code storage is located at the base of the
memory map and supports up to 144 Kbytes (48K
instruction words). Code is stored in three, 48 Kbyte
memory panels that reside on-chip.
Table 2-2
shows
the location and program memory size of each device.
2.4
Data EEPROM Memory
The Data EEPROM array supports up to 4 Kbytes of
data and is located in one memory panel. It is mapped
in program memory space, residing at the end of User
Memory Space (see
Figure 2-2). Table 2-2
shows the
location and size of data EEPROM in each device.
TABLE 2-2:
Device
dsPIC30F2010
dsPIC30F2011
dsPIC30F2012
dsPIC30F3010
dsPIC30F3011
dsPIC30F3012
dsPIC30F3013
dsPIC30F3014
dsPIC30F4011
dsPIC30F4012
dsPIC30F4013
dsPIC30F5011
dsPIC30F5013
dsPIC30F5015
dsPIC30F5016
dsPIC30F6010
dsPIC30F6010A
dsPIC30F6011
dsPIC30F6011A
dsPIC30F6012
dsPIC30F6012A
dsPIC30F6013
dsPIC30F6013A
dsPIC30F6014
dsPIC30F6014A
dsPIC30F6015
CODE MEMORY AND DATA EEPROM MAP AND SIZE
Code Memory map
(Size in Instruction Words)
0x000000-0x001FFE (4K)
0x000000-0x001FFE (4K)
0x000000-0x001FFE (4K)
0x000000-0x003FFE (8K)
0x000000-0x003FFE (8K)
0x000000-0x003FFE (8K)
0x000000-0x003FFE (8K)
0x000000-0x003FFE (8K)
0x000000-0x007FFE (16K)
0x000000-0x007FFE (16K)
0x000000-0x007FFE (16K)
0x000000-0x00AFFE (22K)
0x000000-0x00AFFE (22K)
0x000000-0x00AFFE (22K)
0x000000-0x00AFFE (22K)
0x000000-0x017FFE (48K)
0x000000-0x017FFE (48K)
0x000000-0x015FFE (44K)
0x000000-0x015FFE (44K)
0x000000-0x017FFE (48K)
0x000000-0x017FFE (48K)
0x000000-0x015FFE (44K)
0x000000-0x015FFE (44K)
0x000000-0x017FFE (48K)
0x000000-0x017FFE (48K)
0x000000-0x017FFE (48K)
Data EEPROM Memory Map
(Size in Bytes)
0x7FFC00-0x7FFFFE (1K)
None (0K)
None (0K)
0x7FFC00-0x7FFFFE (1K)
0x7FFC00-0x7FFFFE (1K)
0x7FFC00-0x7FFFFE (1K)
0x7FFC00-0x7FFFFE (1K)
0x7FFC00-0x7FFFFE (1K)
0x7FFC00-0x7FFFFE (1K)
0x7FFC00-0x7FFFFE (1K)
0x7FFC00-0x7FFFFE (1K)
0x7FFC00-0x7FFFFE (1K)
0x7FFC00-0x7FFFFE (1K)
0x7FFC00-0x7FFFFE (1K)
0x7FFC00-0x7FFFFE (1K)
0x7FF000-0x7FFFFE (4K)
0x7FF000-0x7FFFFF (4K)
0x7FF800-0x7FFFFE (2K)
0x7FF800-0x7FFFFE (2K)
0x7FF000-0x7FFFFE (4K)
0x7FF000-0x7FFFFE (4K)
0x7FF800-0x7FFFFE (2K)
0x7FF800-0x7FFFFE (2K)
0x7FF000-0x7FFFFE (4K)
0x7FF000-0x7FFFFE (4K)
0x7FF000-0x7FFFFE (4K)
DS70102K-page 2
©
2010 Microchip Technology Inc.
dsPIC30F Flash Programming Specification
FIGURE 2-2:
PROGRAM MEMORY MAP
000000
User Flash
Code Memory
(48K x 24-bit)
017FFE
018000
User Memory
Space
Reserved
Data EEPROM
(2K x 16-bit)
7FEFFE
7FF000
7FFFFE
800000
Executive Code Memory
(Reserved)
8005BE
8005C0
8005FE
800600
Unit ID (32 x 24-bit)
Reserved
Configuration Memory
Space
Configuration Registers
(8 x 16-bit)
F7FFFE
F80000
F8000E
F80010
Reserved
FEFFFE
FF0000
FF0002
FF0004
FFFFFE
Device ID
(2 x 16-bit)
Reserved
Note:
The address boundaries for user Flash code memory and data EEPROM are device-dependent.
©
2010 Microchip Technology Inc.
DS70102K-page 3
dsPIC30F Flash Programming Specification
3.0
3.1
PROGRAMMING EXECUTIVE
APPLICATION
Programming Executive Overview
4.0
CONFIRMING THE CONTENTS
OF EXECUTIVE MEMORY
The programming executive resides in executive
memory and is executed when Enhanced ICSP
Programming mode is entered. The programming exec-
utive provides the mechanism for the programmer (host
device) to program and verify the dsPIC30F, using a
simple command set and communication protocol.
The following capabilities are provided by the
programming executive:
• Read memory
- Code memory and data EEPROM
- Configuration registers
- Device ID
• Erase memory
- Bulk Erase by segment
- Code memory (by row)
- Data EEPROM (by row)
• Program memory
- Code memory
- Data EEPROM
- Configuration registers
• Query
- Blank Device
- Programming executive software version
The programming executive performs the low-level
tasks required for erasing and programming. This
allows the programmer to program the device by
issuing the appropriate commands and data.
The programming procedure is outlined in
Section 5.0
“Device Programming”.
Before programming can begin, the programmer must
confirm that the programming executive is stored in exec-
utive memory. The procedure for this task is illustrated in
Figure 4-1.
First, ICSP mode is entered. The unique application ID
word stored in executive memory is then read. If the
programming executive is resident, the application ID
word is 0xBB, which means programming can resume
as normal. However, if the application ID word is not
0xBB, the programming executive must be
programmed to Executive Code memory using the
method described in
Section 12.0 “Programming the
Programming Executive to Memory”.
Section 11.0 “ICSP™ Mode”
describes the process
for the ICSP programming method.
Section 11.13
“Reading the Application ID Word”
describes the
procedure for reading the application ID word in ICSP
mode.
FIGURE 4-1:
CONFIRMING PRESENCE
OF THE PROGRAMMING
EXECUTIVE
Start
Enter ICSP™ Mode
Read the
Application ID
from Address
0x8005BE
3.2
Programming Executive Code
Memory
Is
Application ID
0xBB?
Yes
Prog. Executive is
Resident in Memory
No
The programming executive is stored in executive code
memory and executes from this reserved region of
memory. It requires no resources from user code
memory or data EEPROM.
Prog. Executive must
be Programmed
3.3
Programming Executive Data RAM
Finish
The programming executive uses the device’s data
RAM for variable storage and program execution. Once
the programming executive has run, no assumptions
should be made about the contents of data RAM.
DS70102K-page 4
©
2010 Microchip Technology Inc.
dsPIC30F Flash Programming Specification
5.0
5.1
DEVICE PROGRAMMING
Overview of the Programming
Process
Once the programming executive has been verified
in memory (or loaded if not present), the dsPIC30F can
be programmed using the command set shown in
Table 5-1.
A detailed description for each command is
provided in
Section 8.0 “Programming Executive
Commands”.
If Advanced Security features are enabled, then
individual Segment Erase operations need to be
performed, based on user selections (i.e., based on the
specific needs of the user application). The specific
operations that are used typically depend on the order
in which various segments need to be programmed for
a given application or system.
Section 5.2 “Entering Enhanced ICSP Mode”
through
Section 5.8 “Exiting Enhanced ICSP Mode”
describe the programming process in detail.
TABLE 5-1:
Command
SCHECK
READD
READP
PROGD
PROGP
PROGC
ERASEB
ERASED
ERASEP
QBLANK
QVER
COMMAND SET SUMMARY
Description
Sanity check
Read data EEPROM, Configuration
registers and device ID
Read code memory
Program one row of data EEPROM
and verify
Program one row of code memory and
verify
Program Configuration bits and verify
Bulk Erase, or erase by segment
Erase data EEPROM
Erase code memory
Query if the code memory and data
EEPROM are blank
Query the software version
FIGURE 5-1:
PROGRAMMING FLOW
Start
Enter Enhanced
ICSP™ mode
Perform Chip
Erase
Program
Configuration
registers to
default value
Program and
verify code
A high-level overview of the programming process is
illustrated in
Figure 5-1.
The process begins by enter-
ing Enhanced ICSP mode. The chip is then bulk
erased, which clears all memory to ‘1’ and allows the
device to be programmed. The Chip Erase is verified
before programming begins. Next, the code memory,
data Flash and Configuration bits are programmed. As
these memories are programmed, they are each
verified to ensure that programming was successful. If
no errors are detected, the programming is complete
and Enhanced ICSP mode is exited. If any of the
verifications fail, the procedure should be repeated,
starting from the Chip Erase.
Program and
verify data
Program and verify
Configuration bits
Exit Enhanced ICSP
Mode
Finish
©
2010 Microchip Technology Inc.
DS70102K-page 5
京公网安备 11010802033920号
EEWORLD
