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CY7C1021CV33-15ZXCT

Description
IC sram 1mbit 15ns 44tsop
Categorystorage   
File Size295KB,14 Pages
ManufacturerCypress Semiconductor
Environmental Compliance  
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CY7C1021CV33-15ZXCT Overview

IC sram 1mbit 15ns 44tsop

CY7C1021CV33-15ZXCT Parametric

Parameter NameAttribute value
Datasheets
CY7C1021CV33
Product Photos
44-TSOP Pkg
Standard Package1,000
CategoryIntegrated Circuits (ICs)
FamilyMemory
PackagingTape & Reel (TR)
Format - MemoryRAM
Memory TypeSRAM - Asynchronous
Memory Size1M (64K x 16)
Speed15ns
InterfaceParallel
Voltage - Supply3 V ~ 3.6 V
Operating Temperature0°C ~ 70°C
Package / Case44-TSOP (0.400", 10.16mm Width)
Supplier Device Package44-TSOP II
CY7C1021CV33
1-Mbit (64K x 16) Static RAM
Features
Functional Description
The CY7C1021CV33 is a high performance CMOS static RAM
organized as 65,536 words by 16 bits. This device has an
automatic power down feature that significantly reduces power
consumption when deselected.
Writing to the device is accomplished by taking Chip Enable (CE)
and Write Enable (WE) inputs LOW. If Byte Low Enable (BLE) is
LOW, then data from IO pins (IO
1
through IO
8
), is written into the
location specified on the address pins (A
0
through A
15
). If Byte
High Enable (BHE) is LOW, then data from IO pins (IO
9
through
IO
16
) is written into the location specified on the address pins (A
0
through A
15
).
Reading from the device is accomplished by taking Chip Enable
(CE) and Output Enable (OE) LOW while forcing the Write
Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data
from the memory location specified by the address pins appear
on IO
1
to IO
8
. If Byte High Enable (BHE) is LOW, then data from
memory appears on IO
9
to IO
16
. For more information, see the
“Truth Table”
on page 9 for a complete description of Read and
Write modes.
The input and output pins (IO
1
through IO
16
) are placed in a high
impedance state when the device is deselected (CE HIGH), the
outputs are disabled (OE HIGH), the BHE and BLE are disabled
(BHE, BLE HIGH), or during a write operation (CE LOW and WE
LOW).
For best practice recommendations, refer to the Cypress
application note
AN1064, SRAM System Guidelines.
Temperature ranges
Commercial: 0°C to 70°C
Industrial: –40°C to 85°C
Automotive-A: –40°C to 85°C
Automotive-E: –40°C to 125°C
Pin and function compatible with CY7C1021BV33
High speed
t
AA
= 8 ns (Commercial)
t
AA
= 10 ns (Industrial and Automotive-A)
t
AA
= 12 ns (Automotive-E)
CMOS for optimum speed and power
Low active power: 325 mW (max)
Automatic power down when deselected
Independent control of upper and lower bits
Available in Pb-free and non Pb-free 44-pin 400 Mil SOJ, 44-pin
TSOP II and 48-Ball FBGA packages
Logic Block Diagram
DATA IN DRIVERS
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
ROW DECODER
64K x 16
RAM Array
SENSE AMPS
IO
0
–IO
7
IO
8
–IO
15
COLUMN DECODER
BHE
WE
CE
OE
BLE
A
8
A
9
A
10
A
11
A
12
A
13
A
14
A
15
Cypress Semiconductor Corporation
Document Number: 38-05132 Rev. *I
198 Champion Court
San Jose
,
CA 95134-1709
408-943-2600
Revised January 04, 2008
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CY7C1021CV33-15ZXCT Related Products

CY7C1021CV33-15ZXCT CY7C1021CV33-12ZXCT CY7C1021CV33-10ZXCT CY7C1021CV33-15ZSXAT
Description IC sram 1mbit 15ns 44tsop IC sram 1mbit 12ns 44tsop IC sram 1mbit 10ns 44tsop IC sram 1mbit 15ns 44tsop
Standard Package 1,000 1,000 1,000 1,000
Category Integrated Circuits (ICs) Integrated Circuits (ICs) Integrated Circuits (ICs) Integrated Circuits (ICs)
Family Memory Memory Memory Memory
Packaging Tape & Reel (TR) Tape & Reel (TR) Tape & Reel (TR) Tape & Reel (TR)
Format - Memory RAM RAM RAM RAM
Memory Type SRAM - Asynchronous SRAM - Asynchronous SRAM - Asynchronous SRAM - Asynchronous
Memory Size 1M (64K x 16) 1M (64K x 16) 1M (64K x 16) 1M (64K x 16)
Speed 15ns 12ns 10ns 15ns
Interface Parallel Parallel Parallel Parallel
Voltage - Supply 3 V ~ 3.6 V 3 V ~ 3.6 V 3 V ~ 3.6 V 3 V ~ 3.6 V
Operating Temperature 0°C ~ 70°C 0°C ~ 70°C 0°C ~ 70°C -40°C ~ 85°C
Package / Case 44-TSOP (0.400", 10.16mm Width) 44-TSOP (0.400", 10.16mm Width) 44-TSOP (0.400", 10.16mm Width) 44-TSOP (0.400", 10.16mm Width)
Supplier Device Package 44-TSOP II 44-TSOP II 44-TSOP II 44-TSOP II

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