IDT71T75602S200PFG8 datasheet, PDF

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IDT71T75602S200PFG8: DescriptionIC sram 18mbit 200mhz 100tqfp; Categorystorage; File Size401KB，23 Pages; ManufacturerIDT (Integrated Device Technology, Inc.); Websitehttp://www.idt.com/; Environmental Compliance

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IDT71T75602S200PFG8 Overview

IC sram 18mbit 200mhz 100tqfp

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512K x 36, 1M x 18

2.5V Synchronous ZBT™ SRAMs

2.5V I/O, Burst Counter

Pipelined Outputs

• 512K x 36, 1M x 18 memory configurations

• Supports high performance system speed - 200 MHz

(3.2 ns Clock-to-Data Access)

• ZBT

Feature - No dead cycles between write and read

cycles

• Internally synchronized output buffer enable eliminates the

need to control

• Single R/W (READ/WRITE) control pin

• Positive clock-edge triggered address, data, and control

signal registers for fully pipelined applications

• 4-word burst capability (interleaved or linear)

• Individual byte write (BW

) control (May tie active)

• Three chip enables for simple depth expansion

• 2.5V power supply (±5%)

• 2.5V I/O Supply (V

DDQ

)

• Power down controlled by ZZ input

• Boundary Scan JTAG Interface (IEEE 1149.1 Compliant)

• Packaged in a JEDEC standard 100-pin plastic thin quad

flatpack (TQFP), 119 ball grid array (BGA)

IDT71T75602

IDT71T75802

Features

The IDT71T75602/802 are 2.5V high-speed 18,874,368-bit

(18 Megabit) synchronous SRAMs. They are designed to eliminate dead

bus cycles when turning the bus around between reads and writes, or

writes and reads. Thus, they have been given the name ZBT

, or Zero

Bus Turnaround.

Address and control signals are applied to the SRAM during one

clock cycle, and two cycles later the associated data cycle occurs, be it

read or write.

The IDT71T75602/802 contain data I/O, address and control signal

registers. Output enable is the only asynchronous signal and can be used

to disable the outputs at any given time.

A Clock Enable

CEN

pin allows operation of the IDT71T75602/802

to be suspended as long as necessary. All synchronous inputs are ignored

when (CEN) is high and the internal device registers will hold their previous

values.

There are three chip enable pins (CE

, CE

) that allow the

user to deselect the device when desired. If any one of these three is not

asserted when ADV/LD is low, no new memory operation can be initiated.

However, any pending data transfers (reads or writes) will be completed.

Description

Pin Description Summary

-A

, CE

R/W

CEN

CLK

ADV/LD

LBO

TMS

TDI

TCK

TDO

TRST

I/O

-I/O

, I/O

-I/O

, V

DDQ

Address Inputs

Chip Enables

Output Enable

Read/Write Signal

Clock Enable

Individual Byte Write Selects

Clock

Advance burst address / Load new address

Linear / Interleaved Burst Order

Test Mode Select

Test Data Input

Test Clock

Test Data Input

JTAG Reset (Optional)

Sleep Mode

Data Input / Output

Core Power, I/O Power

Ground

Input

Output

Input

I/O

Supply

Synchronous

Asynchronous

Synchronous

N/A

Synchronous

Static

N/A

Asynchronous

Synchronous

Static

APRIL 2012

DSC-5313/10

5313 tbl 01

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Shortcut: 00 01 02 03 04 05 06 07 08 09 0A 0C 0F 0J 0L 0M 0R 0S 0T 0Z 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 1H 1K 1M 1N 1P 1S 1T 1V 1X 1Z 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 2G 2K 2M 2N 2P 2Q 2R 2S 2T 2W 2Z 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F 3G 3H 3J 3K 3L 3M 3N 3P 3R 3S 3T 3V 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4M 4N 4P 4S 4T 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5E 5G 5H 5K 5M 5N 5P 5S 5T 5V 60 61 62 63 64 65 66 67 68 69 6A 6C 6E 6F 6M 6N 6P 6R 6S 6T 70 71 72 73 74 75 76 77 78 79 7A 7B 7C 7M 7N 7P 7Q 7V 7W 7X 80 81 82 83 84 85 86 87 88 89 8A 8D 8E 8L 8N 8P 8S 8T 8W 8Y 8Z 90 91 92 93 94 95 96 97 98 99 9A 9B 9C 9D 9F 9G 9H 9L 9S 9T 9W

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