A6810
10-Bit Serial Input Latched Source Driver
Discontinued Product
This device is no longer in production. The device should not be
purchased for new design applications. Samples are no longer available.
Date of status change: November 1, 2010
Recommended Substitutions:
For existing customer transition, and for new customers or new appli-
cations, contact Allegro Sales.
NOTE: For detailed information on purchasing options, contact your
local Allegro field applications engineer or sales representative.
Allegro MicroSystems, Inc. reserves the right to make, from time to time, revisions to the anticipated product life cycle plan
for a product to accommodate changes in production capabilities, alternative product availabilities, or market demand. The
information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, Inc. assumes no respon-
sibility for its use; nor for any infringements of patents or other rights of third parties which may result from its use.
A6810
10-Bit Serial Input Latched Source Driver
Features and Benefits
▪
Controlled output slew rate
▪
High-speed data storage
▪
60 V minimum output breakdown
▪
High data-input rate
▪
PNP active pull-downs
▪
Low output-saturation voltages
▪
Low-power CMOS logic and latches
▪
Improved replacements for TL4810x, UCN5810x, and
UCQ5810x
Description
The A6810 combines 10-bit CMOS shift registers,
accompanying data latches, and control circuitry with bipolar
sourcing outputs and PNP active pull-downs. Designed
primarily to drive vacuum-fluorescent (VF) displays, the 60 V
and –40 mA output ratings also allow this device to be used in
many other peripheral power driver applications. The A6810
features an increased data input rate (compared with the older
UCN/UCQ5810-F) and a controlled output slew rate.
The CMOS shift register and latches allow direct interfacing
with microprocessor-based systems. With a 3.3 or 5 V logic
supply, serial data-input rates of at least 10 MHz can be
attained
A CMOS serial data output permits cascaded connections in
applications requiring additional drive lines. Similar devices
are available as the A6812 (20-bit) and A6818 (32-bit).
Packages:
18-pin DIP
(A package)
20-pin SOICW
(LW package)
The A6810 output source drivers are NPN Darlingtons, capable
of sourcing up to 40 mA. The controlled output slew rate reduces
electromagnetic noise, which is an important consideration in
systems that include telecommunications and microprocessors,
and to meet government emissions regulations. For inter-digit
Not to scale
Continued on the next page…
Functional Block Diagram
26182.124I
A6810
10-Bit Serial Input Latched Source Driver
Description (continued)
blanking, all output drivers can be disabled and all sink drivers
turned on with a BLANKING input high. The PNP active pull-
downs can sink at least 2.5 mA.
The A6810 is available in three temperature ranges for optimum
performance in commercial (S), industrial (E), and automotive (K)
applications. It is provided in two package styles, through-hole
DIP (package A) and surface-mount SOIC (package LW). Copper
leadframes, low logic-power dissipation, and low output-saturation
voltages allow all devices to source 25 mA from all outputs
continuously over the full operating temperature range.
The lead (Pb) free versions have 100% matte tin leadframe
plating.
Selection Guide
Part Number
A6810EA-T
A6810SA-T
A6810ELWTR-T
A6810KLWTR-T
Pb-free
Yes
Yes
Yes
Yes
Packing
21 pieces/tube
21 pieces/tube
1000 pieces/13-in. reel
1000 pieces/13-in. reel
Ambient Temperature, T
A
(°C)
–40 to 85
–20 to 85
–40 to 85
–40 to 125
20-pin SOIC-W
Package
18-pin DIP
A6810SLWTR-T
Yes
1000 pieces/13-in. reel
–20 to 85
*Variant is in production but has been determined to be LAST TIME BUY. This classification indicates that the variant is obsolete and
notice has been given. Sale of the variant is currently restricted to existing customer applications. The variant should not be purchased
for new design applications because of obsolescence in the near future. Samples are no longer available. Status date change May 3,
2010. Deadline for receipt of LAST TIME BUY orders is October 29, 2010.
Absolute Maximum Ratings*
Characteristic
Logic Supply Voltage
Driver Supply Voltage
Input Voltage Range
Continuous Output Current Range
Operating Ambient Temperature
Maximum Junction Temperature
Storage Temperature
Symbol
V
DD
V
BB
V
IN
I
OUT
Range E
T
A
T
J
(max)
T
stg
Range K
Range S
Notes
Rating
7.0
60
–0.3 to V
DD
+ 0.3
–40 to 15
–40 to 85
–40 to 125
–20 to 85
150
–55 to 125
Units
V
V
V
mA
ºC
ºC
ºC
ºC
ºC
*Caution: These CMOS devices have input static protection (Class 2) but are still susceptible to damage if exposed to extremely high
static electrical charges.
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
2
A6810
10-Bit Serial Input Latched Source Driver
Pin-out Diagrams
Thermal Characteristics
Characteristic
Package Thermal Resistance
Symbol
R
θJA
Test Conditions*
Package A, 1-layer PCB with copper limited to solder pads
Package LW, 1-layer PCB with copper limited to solder pads
Value Units
65
90
ºC/W
ºC/W
*Additional thermal information available on the Allegro website.
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
3
A6810
10-Bit Serial Input Latched Source Driver
ELECTRICAL CHARACTERISTICS at T
A
= +25°C (A6810S-) or over operating temperature range (A6810E-),
V
BB
= 60 V, logic supply operating voltage V
DD
= 3.0 to 5.5 V; unless otherwise noted
Limits @ V
DD
= 3.3 V
Characteristic
Output Leakage Current
Output Voltage
Symbol
I
CEX
V
OUT(1)
V
OUT(0)
Output Pull-Down Current
Input Voltage
I
OUT(0)
V
IN(1)
V
IN(0)
Input Current
I
IN(1)
I
IN(0)
Input Clamp Voltage
Serial Data Output Voltage
V
IK
V
OUT(1)
V
OUT(0)
Maximum Clock Frequency
Logic Supply Current
f
c
I
DD(1)
I
DD(0)
Load Supply Current
I
BB(1)
I
BB(0)
Blanking-to-Output Delay
t
dis(BQ)
t
en(BQ)
Strobe-to-Output Delay
t
p(STH-QL)
t
p(STH-QH)
Output Fall Time
Output Rise Time
Output Slew Rate
t
f
t
r
dV/dt
All Outputs High
All Outputs Low
All Outputs High, No Load
All Outputs Low
C
L
= 30 pF, 50% to 50%
C
L
= 30 pF, 50% to 50%
R
L
= 2.3 kΩ, C
L
≤
30 pF
R
L
= 2.3 kΩ, C
L
≤
30 pF
R
L
= 2.3 kΩ, C
L
≤
30 pF
R
L
= 2.3 kΩ, C
L
≤
30 pF
R
L
= 2.3 kΩ, C
L
≤
30 pF
I
OUT
= ±200
μA
V
IN
= V
DD
V
IN
= 0 V
I
IN
= -200
μA
I
OUT
= -200
μA
I
OUT
= 200
μA
Test Conditions
V
OUT
= 0 V
I
OUT
= -25 mA
I
OUT
= 1 mA
V
OUT
= 5 V to V
BB
Mln.
—
57.5
—
2.5
2.2
—
—
—
—
2.8
—
10*
—
—
—
—
—
—
—
—
2.4
2.4
4.0
—
Typ.
<-0.1
58.3
1.0
5.0
—
—
<0.01
<-0.01
-0.8
3.05
0.15
—
0.25
0.25
1.5
0.2
0.7
1.8
0.7
1.8
—
—
—
50
Max.
-15
—
1.5
—
—
1.1
1.0
-1.0
-1.5
—
0.3
—
0.75
0.75
3.0
20
2.0
3.0
2.0
3.0
12
12
20
—
Limits @ V
DD
= 5 V
Min.
—
57.5
—
2.5
3.3
—
—
—
—
4.5
—
10*
—
—
—
—
—
—
—
—
2.4
2.4
4.0
—
Typ.
<-0.1
58.3
1.0
5.0
—
—
<0.01
<-0.01
-0.8
4.75
0.15
—
0.3
0.3
1.5
0.2
0.7
1.8
0.7
1.8
—
—
—
50
Max.
-15
—
1.5
—
—
1.7
1.0
-1.0
-1.5
—
0.3
—
1.0
1.0
3.0
20
2.0
3.0
2.0
3.0
12
12
20
—
Units
μA
V
V
mA
V
V
μA
μA
V
V
V
MHz
mA
mA
mA
μA
μs
μs
μs
μs
μs
μs
V/μs
ns
Clock-to-Serial Data Out Delay t
p(CH-SQX)
Negative current is defined as coming out of (sourcing) the specified device terminal.
Typical data is is for design information only and is at T
A
= +25°C.
*Operation at a clock frequency greater than the specified minimum value is possible but not warranteed.
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
4
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