5962-9759802QXC datasheet, PDF

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5962-9759802QXC: DescriptionFlash PLD, 19ns, 128-Cell, CMOS, CPGA84, CAVITY-UP, CERAMIC, PGA-84; CategoryProgrammable logic devices Programmable logic; File Size131KB，9 Pages; ManufacturerCypress Semiconductor

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5962-9759802QXC Overview

Flash PLD, 19ns, 128-Cell, CMOS, CPGA84, CAVITY-UP, CERAMIC, PGA-84

5962-9759802QXC Parametric

Parameter Name	Attribute value
Parts packaging code	PGA
package instruction	PGA, PGA84M,11X11
Contacts	84
Reach Compliance Code	unknown
ECCN code	3A001.A.2.C
Other features	YES
maximum clock frequency	67.5 MHz
In-system programmable	YES
JESD-30 code	S-CPGA-P84
JESD-609 code	e4
JTAG BST	NO
Dedicated input times	1
Number of I/O lines	64
Number of macro cells	128
Number of terminals	84
Maximum operating temperature	125 °C
Minimum operating temperature	-55 °C
organize	1 DEDICATED INPUTS, 64 I/O
Output function	MACROCELL
Package body material	CERAMIC, METAL-SEALED COFIRED
encapsulated code	PGA
Encapsulate equivalent code	PGA84M,11X11
Package shape	SQUARE
Package form	GRID ARRAY
power supply	5 V
Programmable logic type	FLASH PLD
propagation delay	19 ns
Certification status	Not Qualified
Filter level	MIL-PRF-38535 Class Q
Maximum supply voltage	5.5 V
Minimum supply voltage	4.5 V
Nominal supply voltage	5 V
surface mount	NO
technology	CMOS
Temperature level	MILITARY
Terminal surface	GOLD
Terminal form	PIN/PEG
Terminal pitch	2.54 mm
Terminal location	PERPENDICULAR
Base Number Matches	1

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LASH

370i™ ISR™

CPLD Family

UltraLogic™ High-Density Flash CPLDs

Features

• Flash In-System Reprogrammable (ISR™) CMOS

CPLDs

— Combines on board reprogramming with pinout flex-

ibility and a simple timing model

— Design changes don’t cause pinout or timing chang-

— JTAG interface

• High density

— 32–128 macrocells

— 32–128 I/O pins

•

— Multiple clock pins

Fully PCI compliant

Bus Hold capabilities on all I/Os and dedicated inputs

3.3-V or 5.0-V I/O operation on all devices

High speed

— t

= 8.5–10 ns

— t

= 5–7 ns

— t

= 6–7 ns

• Fast Programmable Interconnect Matrix (PIM)

— Uniform predictable delay, independent of routing

• Intelligent product term allocator

— 0–16 product terms to any macrocell

— Provides product term steering on an individual ba-

sis

— Provides product term sharing among local macro-

cells

• Simple timing model

— No fanout delays

— No expander delays

— No dedicated vs. I/O pin delays

— No additional delay through PIM

— No penalty for using full 16 product terms

— No delay for steering or sharing product terms

• Flexible clocking

— 2–4 clock pins per device

— Clock polarity control

• Security bit and user ID supported

• Packages

— 44–160 pins

— PLCC, CLCC, PGA, CQFP, and TQFP packages

General Description

The F

LASH

370i™ family of CMOS CPLDs provides a range of

high-density programmable logic solutions with unparalleled

performance. Each member of the family is designed with Cy-

press’s state-of-the-art 0.65-micron Flash technology.

All of the UltraLogic F

LASH

370i devices are electrically eras-

able and In-System Reprogrammable (ISR), which simplifies

both design and manufacturing flows, thereby reducing costs.

Because of the superior routability of the F

LASH

370i devices,

ISR allows users to change existing logic designs without

changing pinout assignments or timing. The Cypress ISR

function is implemented through a JTAG serial interface. Data

is shifted in and out through the SDI and SDO pins, respec-

tively. The ISR interface is enabled from the programming volt-

age pin (ISR

). The entire family is fully compliant with the

PCI Local Bus specification, meeting all the electrical and tim-

ing requirements. Also, the entire family features bus-hold ca-

pabilities on all I/Os and dedicated inputs. Additionally, the en-

tire family is security bit and user ID supported (when the

security bit is programmed, all locations cannot be verified).

LASH

370i Selection Guide

Device

371i

372i

373i

374i

375i

Pins

84/100

160

Macrocells

128

Dedicated

Inputs

I/O Pins

128

Flip-Flops

140

Speed (t

)

8.5

Speed (f

MAX

)

143

125

Cypress Semiconductor Corporation

•

3901 North First Street

•

San Jose

•

CA 95134

•

408-943-2600

July 20, 2000

5962-9759802QXC Related Products

	5962-9759802QXC	5962-9759801QXC	5962-9759702QXA
Description	Flash PLD, 19ns, 128-Cell, CMOS, CPGA84, CAVITY-UP, CERAMIC, PGA-84	Flash PLD, 24ns, 128-Cell, CMOS, CPGA84, CAVITY-UP, CERAMIC, PGA-84	Flash PLD, 15ns, 64-Cell, CMOS, CQCC44, CERAMIC, LCC-44
Parts packaging code	PGA	PGA	LCC
package instruction	PGA, PGA84M,11X11	PGA, PGA84M,11X11	CERAMIC, LCC-44
Contacts	84	84	44
Reach Compliance Code	unknown	unknown	not_compliant
ECCN code	3A001.A.2.C	3A001.A.2.C	3A001.A.2.C
Other features	YES	YES	YES
In-system programmable	YES	YES	YES
JESD-30 code	S-CPGA-P84	S-CPGA-P84	S-CQCC-J44
JESD-609 code	e4	e4	e0
JTAG BST	NO	NO	NO
Dedicated input times	1	1	3
Number of I/O lines	64	64	32
Number of macro cells	128	128	64
Number of terminals	84	84	44
Maximum operating temperature	125 °C	125 °C	125 °C
Minimum operating temperature	-55 °C	-55 °C	-55 °C
organize	1 DEDICATED INPUTS, 64 I/O	1 DEDICATED INPUTS, 64 I/O	3 DEDICATED INPUTS, 32 I/O
Output function	MACROCELL	MACROCELL	MACROCELL
Package body material	CERAMIC, METAL-SEALED COFIRED	CERAMIC, METAL-SEALED COFIRED	CERAMIC, METAL-SEALED COFIRED
encapsulated code	PGA	PGA	QCCJ
Encapsulate equivalent code	PGA84M,11X11	PGA84M,11X11	LDCC44,.7SQ
Package shape	SQUARE	SQUARE	SQUARE
Package form	GRID ARRAY	GRID ARRAY	CHIP CARRIER
power supply	5 V	5 V	5 V
Programmable logic type	FLASH PLD	FLASH PLD	FLASH PLD
propagation delay	19 ns	24 ns	15 ns
Certification status	Not Qualified	Not Qualified	Not Qualified
Filter level	MIL-PRF-38535 Class Q	MIL-PRF-38535 Class Q	MIL-PRF-38535 Class Q
Maximum supply voltage	5.5 V	5.5 V	5.5 V
Minimum supply voltage	4.5 V	4.5 V	4.5 V
Nominal supply voltage	5 V	5 V	5 V
surface mount	NO	NO	YES
technology	CMOS	CMOS	CMOS
Temperature level	MILITARY	MILITARY	MILITARY
Terminal surface	GOLD	GOLD	Tin/Lead (Sn/Pb) - hot dipped
Terminal form	PIN/PEG	PIN/PEG	J BEND
Terminal pitch	2.54 mm	2.54 mm	1.27 mm
Terminal location	PERPENDICULAR	PERPENDICULAR	QUAD
maximum clock frequency	67.5 MHz	50 MHz	-
Base Number Matches	1	1	-
Maker	-	Cypress Semiconductor	Cypress Semiconductor

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