EEWORLDEEWORLDEEWORLD

Part Number

Search
 PDF

800-010-07C7-25HZ

Description
Circular Connector
CategoryThe connector    The connector   
File Size608KB,4 Pages
ManufacturerGlenair
Websitehttp://www.glenair.com/
Download Datasheet Parametric View All

800-010-07C7-25HZ Overview

Circular Connector

800-010-07C7-25HZ Parametric

Parameter NameAttribute value
Objectid7087412904
Reach Compliance Codecompliant
ECCN codeEAR99
YTEOL8.64
Other featuresSTANDARD: MIL-DTL-38999
Back shell typeSOLID
Body/casing typeRECEPTACLE
Connector typeMIL SERIES CONNECTOR
Contact point genderFEMALE
Contact part number809-204
Number of contacts5
Contact size20HD
Coupling typeTHREADED
rotation120
empty shellNO
Environmental characteristicsENVIRONMENT RESISTANT
Filter functionNO
Plug informationMULTIPLE MATING PARTS AVAILABLE
Mixed contactsNO
Installation typeCABLE AND PANEL
Maximum operating temperature200 °C
Minimum operating temperature-65 °C
OptionsGENERAL PURPOSE
polarizationZ
Shell surfaceBLACK ANODIZED
Shell materialALUMINIUM ALLOY
Housing size7
Termination typeCRIMP
Total number of contacts5
Unique insertion number7-25
Using PADS logic to draw schematics
[color=#000000] It has been five years since I registered eeworld in 2008. During this time, I downloaded a lot of things from the forum. However, due to personal reasons, I learned very little knowle...
heningbo PCB Design
How does an application obtain the path of an associated file? ? (Urgent!)
I can associate file types with applications by modifying the registry. That is, when I double-click a video file, I can start my own playback application. But it won't start playing directly. How can...
wangtengfei Embedded System
Can't jump out of while loop
[i] [color=rgb(68, 68, 68)][font=Tahoma,]I use STM8S207C8T6 to write a program, and the development environment is IAR.[/font][/color] [color=rgb(68, 68, 68)][font=Tahoma,]Simulation, flag=0x02, runni...
chenbingjy stm32/stm8
How to generate such waveform using Verilog?
Where input clk output gclk,clk_div output IP0,IP1,IP2,IP3gclk,clk_div is the frequency division output of the reference frequency It is required that on the rising edge of clk_div, IP0, IP1, IP2, and...
eeleader FPGA/CPLD
Various software filters collected and implemented by individuals (such as AD, frequency measurement)
[i=s]This post was last edited by paulhyde on 2014-9-15 09:00[/i]...
Itachi80 Electronics Design Contest
Looking to buy an unused TI DSP C2000 board! (Already purchased!!)
[i=s]This post was last edited by hwc5201314 on 2015-7-12 22:16[/i] [size=6]Has been purchased!! [/size]...
hwc5201314 Buy&Sell

EEWorld
subscription
account

EEWorld
service
account

Automotive
development
circle

Robot
development
community

Index Files: 186  241  1090  748  366  4  5  22  16  8 
Datasheet   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Room 1530, 15th Floor, Building B, No. 18 Zhongguancun Street, Haidian District, Beijing Telephone: (010) 82350740 Postal Code: 100190
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved 京ICP证060456号 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号