unless otherwise noted. Where relevant, specifications apply to both left and right input/output channels.
PCM1700U/U-J/U-K, PCM1700P/P-J/P-K
PARAMETER
RESOLUTION
DYNAMIC RANGE
INPUT
DIGITAL INPUT
Logic Family
Logic Level: V
IH
V
IL
I
IH
I
IL
Data Format
Input Clock Frequency
DYNAMIC CHARACTERISTICS
TOTAL HARMONIC DISTORTION + N
(6)
PCM1700_:
f = 991kHz (0dB)
f = 991kHz (–20dB)
f
IN
= 991kHz (–60dB)
PCM1700_-J:
f = 991kHz (0dB)
f = 991kHz (–20dB)
f = 991kHz (–60dB)
PCM1700_-K:
f = 991kHz (0dB)
f = 991kHz (–20dB)
f = 991kHz (–60dB)
CHANNEL SEPARATION
SIGNAL-TO-NOISE RATIO
(5)
TRANSFER CHARACTERISTICS
ACCURACY
Gain Error
Gain Mismatch
Bipolar Zero Error
BPZ Error Mismatch
BPZ Differential Linearity Error
(7)
Gain Drift
Bipolar Zero Drift
Warm-up Time
POWER SUPPLY REJECTION
ANALOG OUTPUT
Voltage: Output Range
Output Impedance
Current Output
Capacitive Load Drive
Short Circuit Duration
Settling Time
Glitch Energ
Current:
Output Range
Output Impedance
POWER SUPPLY REQUIREMENTS
±V
CC
Supply Voltage
Supply Current: +I
CC
–I
CC
Power Dissipation
TEMPERATURE RANGE
Specification
Operating
Storage
0
–30
–60
+70
+70
+100
°C
°C
°C
+4.75
+V
CC
= +5.0V
–V
CC
= –5.0V
±V
CC
=
±5.0V
+5.00
+18
–42
280
+5.25
+30
–65
475
V
mA
mA
mW
±1
±1
10
5
±1
100
20
1
±V
CC
to V
OUT
+86
±3
±3
%
%
mV
mV
LSB
ppm/°C
ppm of FSR/°C
minute
dB
20Hz to 20kHz at BPZ
(6)
TTL Compatible
+2
0
V
IH
= +2.7V
V
IL
= +0.4V
11.288
Serial BTC
(1)
20
+V
DD
+0.8
+1
–50
V
V
µA
µA
MHz
CONDITIONS
MIN
18
+108
TYP
MAX
UNITS
Bits
dB
f
S
= 352.8kHz
(4)
f
S
= 352.8kHz
f
S
= 352.8kHz
f
S
= 352.8kHz
f
S
= 352.8kHz
f
S
= 352.8kHz
f
S
= 352.8kHz
f
S
= 352.8kHz
f
S
= 352.8kHz
+96
–88
–74
–34
–94
–76
–36
–98
–80
–40
+108
+108
–82
–68
–28
–88
–74
–34
–92
–74
–34
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
Channel to Channel
Channel to Channel
R
LOAD
= 1.5kΩ
(±2%)
(±2%)
±3
V
0.1
Ω
±2
mA
TBD
pF
Indefinite
Sufficient to Meet THD+N Specs
Meets All THD+N Specs Without External Output Deglitching
±670
µA
1.67
kΩ
NOTES: (1) Binary Two’s Complement coding. (6) Ratio of (Distortion
RMS
+ Noise
RMS
) / Signal
RMS
. (3) D/A converter input frequency/signal level on both left and right
channels. (4) D/A converter sample frequency (8 X 44.1kHz; 8X oversampling per channel). (5) Ratio of Noise
RMS
/ Signal
RMS
. Measured using an A-weighted filter.
(6) Bipolar zero. (7) Differential non-linearity at bipolar major carry input code. Measured in 16-bit LSBs. Adjustable to zero error.
®
PCM1700
2
PIN ASSIGNMENTS (Plastic PKG)
PIN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
DESCRIPTION
–5V Analog Supply
Left Channel Servo-Amp Decoupling Point
Left Channel MSB Adjustment
No Connect
Left Channel Bipolar Offset Decoupling Point
Left Channel Current Output
Left Channel Analog Common
Left Channel Summing Junction
Left Channel Voltage Output
No Connect
+5V Digital Supply
Left Channel Data Input
Clock Input
–5V Logic Supply
Latch Enable Input
Right Channel Data Input
Digital Common
No Connect
Right Channel Voltage Output
Right Channel Summing Junction
Right Channel Analog Common
Right Channel Current Output
Right Channel Bipolar Offset Decoupling Point
Right Channel MSB Adjustment
Right Channel Servo-Amp Decoupling Point
MSB Adjustment Potentiometer Voltage Output
+5V Analog Supply
Digital Common
MNEMONIC
–V
CC
CAP
MSB ADJ (L)
NC
CAP
IOUT (L)
ACOM
SJ (L)
VOUT (L)
NC
+V
DD
DATA
CLOCK
–V
DD
LE
DATA (R)
DCOM
NC
VOUT (R)
SJ (R)
ACOM
IOUT (R)
CAP
MSB ADJ (R)
CAP
VPOT
+V
CC
DCOM
PIN ASSIGNMENTS (SOIC PKG)
PIN
9
10
11
19
12
13
14
15
16
17
18
20
21
22
23
24
25
26
27
28
1
2
3
4
5
6
7
8
DESCRIPTION
–5V Analog Supply
Left Channel Servo-Amp Decoupling Point
Left Channel MSB Adjustment
No Connect
Left Channel Bipolar Offset Decoupling Point
Left Channel Current Output
Left Channel Analog Common
Left Channel Summing Junction
Left Channel Voltage Output
No Connect
+5V Digital Supply
Left Channel Data Input
Clock Input
–5V Logic Supply
Latch Enable Input
Right Channel Data Input
Digital Common
No Connect
Right Channel Voltage Output
Right Channel Summing Junction
Right Channel Analog Common
Right Channel Current Output
Right Channel Bipolar Offset Decoupling Point
Right Channel MSB Adjustment
Right Channel Servo-Amp Decoupling Point
MSB Adjustment Potentiometer Voltage Output
+5V Analog Supply
Digital Common
MNEMONIC
–V
CC
CAP
MSB ADJ (L)
NC
CAP
I
OUT
(L)
ACOM
SJ (L)
V
OUT
(L)
NC
+V
DD
DATA
CLOCK
–V
DD
LE
DATA (R)
DCOM
NC
V
OUT
(R)
SJ (R)
ACOM
I
OUT
(R)
CAP
MSB ADJ (R)
CAP
V
POT
+V
DD
DCOM
ORDERING INFORMATION
PCM1700
Basic Model Number
P: Plastic U: SOIC
Performance Grade Code
( ) ( )
NOTE: In the SOIC (PCM1700U) package, the die is rotated 90°. Therefore,
the pin assignments are different from the DIP. See pin assignments on page
4 for details.
PACKAGE INFORMATION
MODEL
PACKAGE
28-Pin SOIC
28-Pin SOIC
28-Pin SOIC
28-Pin Plastic DIP
28-Pin Plastic DIP
28-Pin Plastic DIP
PACKAGE DRAWING
NUMBER
(1)
217
217
217
126
126
126
ABSOLUTE MAXIMUM RATINGS
DC Supply Voltages .....................................................................
±7.5VDC
Input Logic Voltage ................................................................. –1V to +V
CC
Power Dissipation .......................................................................... 500mW
Operating Temperature ..................................................... –25°C to +70°C
Storage Temperature ...................................................... –60°C to +100°C
Lead Temperature (soldering, 10s) ................................................ +300°C
PCM1700U
PCM1700U-J
PCM1700U-K
PCM1700P
PCM1700P-J
PCM1700P-K
NOTE: (1) For detailed drawing and dimension table, please see end of data
sheet, or Appendix D of Burr-Brown IC Data Book.
®
3
PCM1700
> 25ns
Data Input
LSB
> 15ns > 15ns
> 5ns
Clock In
> 25ns
> 25ns
> 60ns
> 15ns
Latch
Enable
> One Clock Cycle
> One Clock Cycle
MSB
DIGITAL INPUT
Binary Two’s
Complement (BTC)
1FFFF Hex
00000 Hex
3FFFF Hex
20000 Hex
DAC Output
+ FS
BPZ
BPZ – 1LSB
– FS
ANALOG OUTPUT
Voltage (V)
V
OUT
Mode
+2.99997711
0.00000000
–0.00002289
–3.00000000
Current (mA)
I
OUT
Mode
–0.66999489
0.00000000
+0.00000511
+0.67000000
TABLE I. PCM1700 Input/Output Relationships.
FIGURE 1. PCM1700P Setup and Hold Timing Diagram.
P13
(Clock)
P12
Data (L)
P16
Data (R)
P15
(Latch
Enable)
1
MSB
2
3
4
10 11 12 13 14 15 16 17 18 19
LSB
1
MSB
2
3
4
10 11 12 13 14 15 16 17 18 19
LSB
FIGURE 2. Timing Diagram.
The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes
no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change
without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant
any BURR-BROWN product for use in life support devices and/or systems.
®
PCM1700
4
+5V
10µF
+
100kΩ
0.01µF
–5V
10µF
0.47µF
0.1µF
1
2
3
4
5
6
7
8
9
10
11
0.47µF
12
13
14
0.47µF
–V
CC
CAP
MSB Adj (Left)
NC
CAP
IOUT (Left)
ACOM (Left)
SJ (Left)
VOUT (Left)
NC
+V
DD
DATA (Left)
Clock
–V
DD
DCOM
+V
CC
VPOT
CAP
MSB Adj (Right)
CAP
IOUT (Right)
ACOM (Right)
SJ (Right)
VOUT (Right)
NC
DCOM
DATA (Right)
LE
28
0.47µF
27
26
25
24
23
22
21
20
19
18
17
16
15
0.1µF
0.1µF
100kΩ
.01µF
Optional Bit
Adjust Circuit
100kΩ
100kΩ
0.1µF
FIGURE 3. Voltage Output Connection Diagram (DIP Package Diagram.)
+5V
10µF
+
100kΩ
0.01µF
–5V
10µF
+
0.47µF
0.1µF
4.5kΩ
(1)
0.1µF
1
2
3
4
5
–V
CC
CAP
MSB Adj (Left)
NC
CAP
IOUT (Left)
ACOM (Left)
SJ (Left)
VOUT (Left)
NC
+V
DD
DATA (Left)
Clock
–V
DD
DCOM
+V
CC
VPOT
CAP
MSB Adj (Right)
CAP
IOUT (Right)
ACOM (Right)
SJ (Right)
VOUT (Right)
NC
DCOM
DATA (Right)
LE
28
0.47µF
27
26
25
24
23
22
21
20
19
18
17
16
15
NOTES:
(1) Low TCR resistors
such as Vishay.
1.22kΩ
(1)
BB
OPA602BP
V
OUT
(L)
0.1µF
0.1µF
100kΩ
0.01µF
4.55kΩ
(1)
Optional Bit
Adjust Circuit
100kΩ
100kΩ
V
OUT
(R)
6
7
8
1.22kΩ
(1)
BB
OPA602BP
9
10
11
0 .47µF
12
13
14
0.47µF
FIGURE 4. Current Output Connection Diagram (DIP Package Diagram.)
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