INTEGRATED CIRCUITS
PCK2509S
50–150 MHz 1:9 SDRAM clock driver
Product specification
1999 Oct 19
Philips
Semiconductors
Philips Semiconductors
Product specification
50–150 MHz 1:9 SDRAM clock driver
PCK2509S
FEATURES
•
Phase-Locked Loop Clock distribution for PC100/PC133 SDRAM
applications
•
Spread Spectrum clock compatible
•
Operating frequency 50 to 150 MHz
•
(t
phase error
– jitter) at 100 to133 MHz =
±50
ps
•
Jitter (peak-peak) at 100 to 133 MHz =
±
80 ps
•
Jitter (cycle-cycle) at 100 to 133 MHz = 65 ps
•
Pin-to-pin skew
<
200 ps
•
Available in plastic 24-Pin TSSOP
•
Distributes one clock input to one bank of ten outputs
•
External Feedback (FBIN) terminal Is used to synchronize the
outputs to the clock input
adjusted to 50 percent, independent of the duty cycle at CLK. Each
bank of outputs can be enabled or disabled separately via the
control (1G and 2G) inputs. When the G inputs are high, the outputs
switch in phase and frequency with CLK; when the G inputs are low,
the outputs are disabled to the logic–low state.
Unlike many products containing PLLs, the PCK2509S does not
require external RC networks. The loop filter for the PLL is included
on-chip, minimizing component count, board space, and cost.
Because it is based on PLL circuitry, the PCK2509S requires a
stabilization time to achieve phase lock of the feedback signal to the
reference signal. This stabilization time is required, following power up
and application of a fixed-frequency, fixed-phase signal at CLK, and
following any changes to the PLL reference or feedback signals. The
PLL can be bypassed for test purposes by strapping AV
CC
to ground.
The PCK2509S is characterized for operation from 0°C to +70°C.
PIN CONFIGURATION
AGND
V
CC
1Y0
1Y1
1Y2
GND
1
2
3
4
5
6
7
8
9
24 CLK
23 AV
CC
22 V
CC
21 2Y0
20 2Y1
19 GND
18 GND
17 2Y2
16 2Y3
15 V
CC
14 2G
13 FBIN
•
On-Chip series damping resistors
•
No external RC network required
•
Operates at 3.3 V
•
Inputs compatible with 2.5 V and 3.3 V ranges
DESCRIPTION
The PCK2509S is a high-performance, low-skew, low-jitter,
phase-locked loop (PLL) clock driver. It uses a PLLto precisely align,
in both frequency and phase, the feedback (FBOUT) output to the
clock (CLK) input signal. It is specifically designed for use with
synchronous DRAMs. The PCK2509S operates at 3.3 V V
CC
and is
input compatible with both 2.5 V and 3.3 V input voltage ranges. It
also provides integrated series-damping resistors that make it ideal
for driving point-to-point loads.
One bank of five outputs and one bank of four outputs provide nine
low-skew, low-jitter copies of CLK. Output signal duty cycles are
GND
1Y3
1Y4
V
CC
10
1G 11
FBOUT 12
SW00389
ORDERING INFORMATION
PACKAGES
24-Pin Plastic TSSOP
TEMPERATURE RANGE
0°C to +70°C
ORDER CODE
PCK2509S PW
DRAWING NUMBER
SOT355-1
1999 Oct 19
2
853–2180 22544
Philips Semiconductors
Product specification
50–150 MHz 1:9 SDRAM clock driver
PCK2509S
PIN DESCRIPTIONS
PIN NUMBER
1
2, 10, 15, 22
3, 4, 5, 8, 9
6, 7, 18, 19
11
SYMBOL
AGND
V
CC
1Y (0–4)
GND
1G
TYPE
GND
PWR
OUT
GND
IN
Power supply
Clock outputs.
These outputs provide low-skew copies of CLK. Output bank 1Y(0–4) is enabled
via the1G input. These outputs can be disabled to a logic LOW state by de-asserting the 1G control
input. Each output has an integrated 25
Ω
series-damping resistor.
Ground
Output bank enable.
1G is the output enable for outputs 1Y(0–4). When 1G is LOW, outputs
1Y(0–4) are disabled to a logic LOW state. When 1G is HIGH, all outputs 1Y(0–4) are enabled and
switch at the same frequency as CLK.
Feedback output.
FBOUT is dedicated for external feedback. It switches at the same frequency as
CLK. When externally wired to FBIN, FBOUT completes the feedback loop of the PLL. FBOUT has
an integrated 25
Ω
series-damping resistor.
Feedback input.
FBIN provides the feedback signal to the internal PLL. FBIN must be hard-wired
to FBOUT to complete the PLL. The integrated PLL synchronizes CLK and FBIN so that there is
nominally zero phase error between CLK and FBIN.
Output bank enable.
2G is the output enable for outputs 2Y(0–3). When 2G is LOW, outputs
2Y(0–3) are disabled to a logic LOW state. When 2G is HIGH, all outputs 2Y(0–3) are enabled and
switch at the same frequency as CLK.
Clock outputs.
These outputs provide low-skew copies of CLK. Output bank 2Y(0–3) is enabled
via the 2G input. These outputs can be disabled to a logic LOW state by de-asserting the 2G
control input. Each output has an integrated 25
Ω
series-damping resistor.
Analog power supply.
AV
CC
provides the power reference for the analog circuitry. In addition,
AV
CC
can be used to bypass the PLL for test purposes. When AV
CC
is strapped to ground, PLL is
bypassed and CLK is buffered directly to the device outputs.
Clock input.
CLK provides the clock signal to be distributed by the PCK2509S clock driver. CLK is
used to provide the reference signal to the integrated PLL that generates the clock output signals.
CLK must have a fixed frequency and fixed phase for the PLL to obtain phase lock. Once the circuit
is powered up and a valid CLK signal is applied, a stabilization time is required for the PLL to phase
lock the feedback signal to its reference signal.
NAME, FUNCTION, and DIRECTION
Analog ground.
AGND provides the ground reference for the analog circuitry.
12
FBOUT
OUT
13
FBIN
IN
14
2G
IN
16, 17, 20, 21
2Y (0–3)
OUT
23
AV
CC
PWR
24
CLK
IN
FUNCTION TABLE
INPUTS
1G
X
L
L
H
H
2G
X
L
H
L
H
CLK
L
H
H
H
H
1Y (0–4)
L
L
L
H
H
OUTPUTS
2Y (0–3)
L
L
H
L
H
FBOUT
L
H
H
H
H
1999 Oct 19
3
Philips Semiconductors
Product specification
50–150 MHz 1:9 SDRAM clock driver
PCK2509S
FUNCTIONAL BLOCK DIAGRAM
1G
11
3
1Y0
4
1Y1
5
1Y2
8
9
1Y3
1Y4
2G
14
21
2Y0
20
CLK
FBIN
24
13
PLL
17
2Y1
2Y2
16
AV
CC
23
12
2Y3
FBOUT
SW00388
168-pin SDR SDRAM DIMM
SDRAM
SDRAM
SDRAM
SDRAM
SDRAM
SDRAM
SDRAM
SDRAM
SDRAM
SDRAM
BACK SIDE
SDRAM
SDRAM
SDRAM
SDRAM
SDRAM
SDRAM
SDRAM
FRONT SIDE
A[L]VC
A[L]VC
A[L]VC
PCK2509S
The PLL clock distribution device and A[L]VC registered drivers reduce
signal loads on the memory controller and prevent timing delays and
waveform distortions that would cause unreliable operation
SDRAM
SW00410
1999 Oct 19
4
Philips Semiconductors
Product specification
50–150 MHz 1:9 SDRAM clock driver
PCK2509S
ABSOLUTE MAXIMUM RATINGS
1
In accordance with the Absolute Maximum Rating System (IEC 134)
SYMBOL
AV
CC
V
CC
I
IK
V
I
I
OK
V
O
I
O
T
STG
PARAMETER
Supply voltage range
Supply voltage range
Input clamp current
Input voltage range
Output clamp current
Output voltage range
DC output source or sink current
Storage temperature range
V
I
< 0
Note 3
V
O
> V
CC
or V
O
< 0
Notes 3, 4
V
O
= 0 to V
CC
–65
–0.5
–0.5
CONDITION
Note 2
–0.5
LIMITS
MIN
MAX
< V
CC
+ 0.7
+4.6
–50
6.5
±50
V
CC
+ 0.5
±50
+150
UNIT
V
V
mA
V
mA
V
mA
°C
P
TOT
Power dissipation per package
700
mW
NOTES:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.
2. AV
CC
must not exceed V
CC
3. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
4. This value is limited to 4.6 V maximum.
RECOMMENDED OPERATING CONDITIONS
1
SYMBOL
V
CC
, AV
CC
V
IH
V
IL
V
I
T
amb
PARAMETER
Supply voltage
HIGH level input voltage
LOW level input voltage
Input voltage
Operating ambient temperature range in free air
0
0
CONDITIONS
LIMITS
MIN
3
2
0.8
V
CC
+70
MAX
3.6
UNIT
V
V
V
V
°C
NOTE:
1. Unused inputs must be held high or low to prevent them from floating.
ELECTRICAL CHARACTERISTICS
Over recommended operating free-air temperature range (unless otherwise specified)
SYMBOL
V
IK
V
OH
PARAMETER
Input clamp voltage
HIGH level output voltage
TEST CONDITIONS
AV
CC
, V
CC
(V)
3
MIN to MAX
3
3
MIN to MAX
V
OL
I
I
I
CC
I
CCA
∆I
CC
C
I
C
O
LOW level output voltage
Input current
Quiescent supply current
AV
CC
power supply current
Additional supply current per
input pin
Input capacitance
Output capacitance
3
3
3.6
3.6
AV
CC
= 3.3
3.3 to 3.6
3.3
3.3
One input at V
CC
– 0.6V;
other inputs at V
CC
or GND
V
I
= V
CC
or GND
V
O
= V
CC
or GND
2.8
5.4
OTHER
I
I
= –18mA
I
OH
= – 100µA
I
OH
= – 12mA
I
OH
= – 6mA
I
OL
= 100µA
I
OL
= 12mA
I
OL
= 6mA
V
I
= V
CC
or GND
V
I
= V
CC
or GND;
I
O
= 0, outputs: LOW or HIGH
30
V
CC
– 0.2
2.1
2.4
–
–
–
0.2
0.8
0.55
±5
10
50
500
µA
µA
µA
µA
pF
pF
V
V
MIN
LIMITS
TYP
MAX
–1.2
UNIT
V
1999 Oct 19
5
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