GENERAL DESCRIPTION ..............................................................................................................................................1
1.1
1.1.1
1.1.2
APPLICATIONS FOR THE PCI 9080 .......................................................................................................................2
MAJOR FEATURES..................................................................................................................................................3
COMPATIBILITY OF PCI 9080 WITH PCI 9060, 9060ES, AND 9060SD................................................................4
COMPARISON OF PCI 9060, PCI 9060ES, PCI 9060SD, AND PCI 9080..............................................................5
BUS OPERATION............................................................................................................................................................6
2.1
2.1.1
2.1.2
2.1.2.1
2.1.2.2
2.1.3
PCI BUS CYCLES.....................................................................................................................................................6
Direct Local to PCI Command Codes ............................................................................................................................. 6
LOCAL BUS CYCLES...............................................................................................................................................7
Local Bus Arbitration........................................................................................................................................................... 7
Local Bus Direct Master...................................................................................................................................................... 7
Local Bus Direct Slave........................................................................................................................................................ 7
Ready/Wait State Control ............................................................................................................................................... 7
Wait State—PCI Side ............................................................................................................................................... 8
Recovery States ............................................................................................................................................................. 9
Local Bus Read Accesses .............................................................................................................................................. 9
Local Bus Write Accesses .............................................................................................................................................. 9
Direct Slave Write Accesses—8- and 16-Bit Buses........................................................................................................ 9
Local Bus Data Parity ..................................................................................................................................................... 9
Local Bus Little/Big Endian ............................................................................................................................................. 9
32 Bit Local Bus—Big Endian Mode ......................................................................................................................... 9
16 Bit Local Bus—Big Endian Mode ....................................................................................................................... 10
8 Bit Local Bus—Big Endian Mode ......................................................................................................................... 10
Local Bus Input LRESETi# ............................................................................................................................................... 12
Local Bus Output LRESETo# ........................................................................................................................................... 12
Serial EEPROM Initialization ............................................................................................................................................ 13
Local Initialization ............................................................................................................................................................. 13
3.3
3.3.1
3.3.2
3.3.3
3.3.4
3.3.5
SERIAL EEPROM ...................................................................................................................................................13
Short Serial EEPROM Load.............................................................................................................................................. 13
Long Serial EEPROM Load .............................................................................................................................................. 14
Extra Long Serial EEPROM Load..................................................................................................................................... 16
Recommended Serial EEPROMs ..................................................................................................................................... 16
Programming the Serial EEPROM.................................................................................................................................... 16
PCI Bus Access to Internal Registers ............................................................................................................................... 17
Local Bus Access to Internal Registers ............................................................................................................................ 17
3.5
3.6
3.6.1
RESPONSE TO FIFO FULL/EMPTY......................................................................................................................18
DIRECT DATA TRANSFER MODES......................................................................................................................18
Direct Master Operation (Local Master to PCI Target)...................................................................................................... 18
CFG (PCI Configuration Type 0 or Type 1 Cycles)....................................................................................................... 20
Direct Bus Master Lock................................................................................................................................................. 21
Write and Invalidate ...................................................................................................................................................... 21
DMA Write and Invalidate ....................................................................................................................................... 21
Direct Master Write and Invalidate.......................................................................................................................... 21
3.6.1.1
3.6.1.2
3.6.1.3
3.6.1.4
3.6.1.5
3.6.1.6
3.6.1.7
3.6.1.8
3.6.1.9
3.6.1.9.1
3.6.1.9.2
3.6.2
3.6.2.1
3.6.2.2
Direct Slave Operation (PCI Master to Local Bus Access) ............................................................................................... 23
PCI to Local Address Mapping ..................................................................................................................................... 24
Local Bus Initialization Software ............................................................................................................................. 25
Deadlock and BREQo................................................................................................................................................... 26
Software/Hardware Solution for Systems without Backoff Capability ..................................................................... 27
Software Solutions to Deadlock .............................................................................................................................. 27
Direct Slave Lock.......................................................................................................................................................... 27
Direct Slave Priority .......................................................................................................................................................... 27
DMA Data Transfers ......................................................................................................................................................... 31
Local to PCI Bus DMA Transfer.................................................................................................................................... 31
PCI to Local Bus DMA Transfer.................................................................................................................................... 32
End of Transfer (EOT0# or EOT1#) Input ..................................................................................................................... 33
Local Latency and Pause Timers.................................................................................................................................. 33
3.7.3.1
3.7.3.2
3.7.3.3
3.7.4
3.7.5
3.7.6
3.7.6.1
3.7.6.2
3.7.6.3
3.8
3.9
3.10
3.11
3.12
VENDOR AND DEVICE ID REGISTERS ...............................................................................................................34
USER INPUT AND OUTPUT ..................................................................................................................................34
Local Interrupt Input.................................................................................................................................................. 35
Local Interrupts (LINTo#) .................................................................................................................................................. 36
Local to PCI Doorbell Interrupt.................................................................................................................................. 36
PCI to Local Doorbell Interrupt.................................................................................................................................. 36
Built-In Self Test Interrupt (BIST).............................................................................................................................. 36
Local LSERR# (Local NMI)............................................................................................................................................... 37
3.13
I
2
0 COMPATIBLE MESSAGE UNIT .......................................................................................................................37
O Pointer Management .................................................................................................................................................. 38
Inbound Free List FIFO..................................................................................................................................................... 39
Inbound Post List FIFO ..................................................................................................................................................... 41
Outbound Post List FIFO .................................................................................................................................................. 41
Outbound Post Queue ...................................................................................................................................................... 41
Local Configuration Registers........................................................................................................................................... 51
(PCIBAR0; PCI:10h, LOC:10h) PCI Base Address Register for Memory Accesses to Local, Runtime,
and DMA Registers........................................................................................................................................................... 58
(PCIBAR1; PCI:14h, LOC:14h) PCI Base Address Register for I/O Accesses to Local, Runtime, and
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