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PCI9060: Description12O COMPATIBLE PCI BUS MASTER INTERFACE CHIP FOR ADAPTERS AND EMBEDDED SYSTEMS; File Size1MB，192 Pages; ManufacturerETC

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12O COMPATIBLE PCI BUS MASTER INTERFACE CHIP FOR ADAPTERS AND EMBEDDED SYSTEMS

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PCI 9080 Data Sheet

Version 1.02

July 24, 1997

Website:

http://www.plxtech.com

Email:

apps@plxtech.com

Phone:

408-774-9060

FAX:

408-774-2169

PCI 9080

TABLE OF CONTENTS

GENERAL DESCRIPTION ..............................................................................................................................................1

1.1

1.1.1

1.1.2

APPLICATIONS FOR THE PCI 9080 .......................................................................................................................2

PCI Adapter Cards.............................................................................................................................................................. 2

Embedded Systems............................................................................................................................................................ 2

1.2

1.3

1.3.1

1.3.2

MAJOR FEATURES..................................................................................................................................................3

COMPATIBILITY OF PCI 9080 WITH PCI 9060, 9060ES, AND 9060SD................................................................4

Pin Compatibility ................................................................................................................................................................. 4

Register Compatibility......................................................................................................................................................... 4

1.4

COMPARISON OF PCI 9060, PCI 9060ES, PCI 9060SD, AND PCI 9080..............................................................5

BUS OPERATION............................................................................................................................................................6

2.1

2.1.1

2.1.2

2.1.2.1

2.1.2.2

2.1.3

PCI BUS CYCLES.....................................................................................................................................................6

PCI Target Command Codes.............................................................................................................................................. 6

PCI Master Command Codes ............................................................................................................................................. 6

DMA Master Command Codes ....................................................................................................................................... 6

Direct Local to PCI Command Codes ............................................................................................................................. 6

PCI Arbitration .................................................................................................................................................................... 6

2.2

2.2.1

2.2.2

2.2.3

LOCAL BUS CYCLES...............................................................................................................................................7

Local Bus Arbitration........................................................................................................................................................... 7

Local Bus Direct Master...................................................................................................................................................... 7

Local Bus Direct Slave........................................................................................................................................................ 7

Ready/Wait State Control ............................................................................................................................................... 7

Wait State—Local Side............................................................................................................................................. 7

Wait State—PCI Side ............................................................................................................................................... 8

2.2.3.1

2.2.3.1.1

2.2.3.1.2

2.2.3.2

Burst Mode and Continuous Burst Mode (Bterm “Burst Terminate” Mode)..................................................................... 8

Burst Mode ............................................................................................................................................................... 8

Continuous Burst Mode (Bterm “Burst Terminate” Mode)......................................................................................... 8

Partial Lword Accesses ............................................................................................................................................ 9

2.2.3.2.1

2.2.3.2.2

2.2.3.2.3

2.2.3.3

2.2.3.4

2.2.3.5

2.2.3.6

2.2.3.7

2.2.3.8

Recovery States ............................................................................................................................................................. 9

Local Bus Read Accesses .............................................................................................................................................. 9

Local Bus Write Accesses .............................................................................................................................................. 9

Direct Slave Write Accesses—8- and 16-Bit Buses........................................................................................................ 9

Local Bus Data Parity ..................................................................................................................................................... 9

Local Bus Little/Big Endian ............................................................................................................................................. 9

32 Bit Local Bus—Big Endian Mode ......................................................................................................................... 9

16 Bit Local Bus—Big Endian Mode ....................................................................................................................... 10

8 Bit Local Bus—Big Endian Mode ......................................................................................................................... 10

Page iii

Version 1.01

2.2.3.8.1

2.2.3.8.2

2.2.3.8.3

©PLX

Technology, Inc., 1997

PCI 9080

TABLE OF CONTENTS

FUNCTIONAL DESCRIPTION.......................................................................................................................................12

3.1

3.1.1

3.1.2

3.1.3

3.1.4

3.1.5

RESET ....................................................................................................................................................................12

PCI Bus Input RST# ......................................................................................................................................................... 12

Software Reset LRESETo# .............................................................................................................................................. 12

Local Bus Input LRESETi# ............................................................................................................................................... 12

Local Bus Output LRESETo# ........................................................................................................................................... 12

Software Reset ................................................................................................................................................................. 12

3.2

3.2.1

3.2.2

PCI 9080 INITIALIZATION......................................................................................................................................12

Serial EEPROM Initialization ............................................................................................................................................ 13

Local Initialization ............................................................................................................................................................. 13

3.3

3.3.1

3.3.2

3.3.3

3.3.4

3.3.5

SERIAL EEPROM ...................................................................................................................................................13

Short Serial EEPROM Load.............................................................................................................................................. 13

Long Serial EEPROM Load .............................................................................................................................................. 14

Extra Long Serial EEPROM Load..................................................................................................................................... 16

Recommended Serial EEPROMs ..................................................................................................................................... 16

Programming the Serial EEPROM.................................................................................................................................... 16

3.4

3.4.1

3.4.2

INTERNAL REGISTER ACCESS ...........................................................................................................................16

PCI Bus Access to Internal Registers ............................................................................................................................... 17

Local Bus Access to Internal Registers ............................................................................................................................ 17

3.5

3.6

3.6.1

RESPONSE TO FIFO FULL/EMPTY......................................................................................................................18

DIRECT DATA TRANSFER MODES......................................................................................................................18

Direct Master Operation (Local Master to PCI Target)...................................................................................................... 18

Decode ......................................................................................................................................................................... 19

FIFOs............................................................................................................................................................................ 19

Memory Access ............................................................................................................................................................ 19

IO/CFG Access............................................................................................................................................................. 20

I/O ................................................................................................................................................................................. 20

CFG (PCI Configuration Type 0 or Type 1 Cycles)....................................................................................................... 20

Direct Bus Master Lock................................................................................................................................................. 21

Master/Target Abort...................................................................................................................................................... 21

Write and Invalidate ...................................................................................................................................................... 21

DMA Write and Invalidate ....................................................................................................................................... 21

Direct Master Write and Invalidate.......................................................................................................................... 21

3.6.1.1

3.6.1.2

3.6.1.3

3.6.1.4

3.6.1.5

3.6.1.6

3.6.1.7

3.6.1.8

3.6.1.9

3.6.1.9.1

3.6.1.9.2

3.6.2

3.6.2.1

3.6.2.2

Direct Slave Operation (PCI Master to Local Bus Access) ............................................................................................... 23

PCI 2.1 Mode................................................................................................................................................................ 23

PCI to Local Address Mapping ..................................................................................................................................... 24

Byte Enables .......................................................................................................................................................... 24

Local Bus Initialization Software ............................................................................................................................. 25

PCI Initialization Software....................................................................................................................................... 25

Page iv

Version 1.01

3.6.2.2.1

3.6.2.2.2

3.6.2.2.3

©PLX

Technology, Inc., 1997

PCI 9080

3.6.2.3

3.6.2.3.1

3.6.2.3.2

3.6.2.3.3

3.6.2.4

3.6.3

TABLE OF CONTENTS

Deadlock and BREQo................................................................................................................................................... 26

Backoff.................................................................................................................................................................... 26

Software/Hardware Solution for Systems without Backoff Capability ..................................................................... 27

Software Solutions to Deadlock .............................................................................................................................. 27

Direct Slave Lock.......................................................................................................................................................... 27

Direct Slave Priority .......................................................................................................................................................... 27

3.7

3.7.1

3.7.2

3.7.3

DMA OPERATION ..................................................................................................................................................28

Non-Chaining Mode DMA ................................................................................................................................................. 28

Chaining Mode DMA......................................................................................................................................................... 29

DMA Data Transfers ......................................................................................................................................................... 31

Local to PCI Bus DMA Transfer.................................................................................................................................... 31

PCI to Local Bus DMA Transfer.................................................................................................................................... 32

Unaligned Transfers ..................................................................................................................................................... 32

Demand Mode DMA ......................................................................................................................................................... 32

DMA Priority...................................................................................................................................................................... 33

DMA Arbitration ................................................................................................................................................................ 33

End of Transfer (EOT0# or EOT1#) Input ..................................................................................................................... 33

DMA Abort .................................................................................................................................................................... 33

Local Latency and Pause Timers.................................................................................................................................. 33

3.7.3.1

3.7.3.2

3.7.3.3

3.7.4

3.7.5

3.7.6

3.7.6.1

3.7.6.2

3.7.6.3

3.8

3.9

3.10

3.11

3.12

VENDOR AND DEVICE ID REGISTERS ...............................................................................................................34

DOORBELL REGISTERS .......................................................................................................................................34

MAILBOX REGISTERS...........................................................................................................................................34

USER INPUT AND OUTPUT ..................................................................................................................................34

INTERRUPTS .........................................................................................................................................................35

PCI Interrupts (INTA#) ...................................................................................................................................................... 35

Local Interrupt Input.................................................................................................................................................. 35

Master/Target Abort Interrupt.................................................................................................................................... 35

3.12.1.1

3.12.1.2

3.12.1

3.12.2

Local Interrupts (LINTo#) .................................................................................................................................................. 36

Local to PCI Doorbell Interrupt.................................................................................................................................. 36

PCI to Local Doorbell Interrupt.................................................................................................................................. 36

Built-In Self Test Interrupt (BIST).............................................................................................................................. 36

DMA Channel 0/1 Interrupts ..................................................................................................................................... 36

3.12.2.1

3.12.2.2

3.12.2.3

3.12.2.4

3.12.3

3.12.4

PCI SERR# (PCI NMI) ...................................................................................................................................................... 37

Local LSERR# (Local NMI)............................................................................................................................................... 37

3.13

0 COMPATIBLE MESSAGE UNIT .......................................................................................................................37

Inbound Messages ........................................................................................................................................................... 38

Outbound Messages......................................................................................................................................................... 38

O Pointer Management .................................................................................................................................................. 38

Inbound Free List FIFO..................................................................................................................................................... 39

Page v

Version 1.01

3.13.1

3.13.2

3.13.3

3.13.4

©PLX

Technology, Inc., 1997

PCI 9080

3.13.5

3.13.6

3.13.7

3.13.8

3.13.9

3.13.10

TABLE OF CONTENTS

Inbound Post List FIFO ..................................................................................................................................................... 41

Outbound Post List FIFO .................................................................................................................................................. 41

Outbound Post Queue ...................................................................................................................................................... 41

Inbound Free Queue......................................................................................................................................................... 41

Outbound Free List FIFO .................................................................................................................................................. 41

0 Enable Sequence .................................................................................................................................................... 42

REGISTERS ...................................................................................................................................................................43

4.1

4.1.1

NEW REGISTER DEFINITIONS SUMMARY .........................................................................................................43

Register Differences between PCI 9080 and PCI 9060, PCI 9060ES, and PCI 9060SD.................................................. 44

4.2

4.2.1

4.2.2

4.2.3

4.2.4

4.2.5

REGISTER ADDRESS MAPPING..........................................................................................................................50

PCI Configuration Registers ............................................................................................................................................. 50

Local Configuration Registers........................................................................................................................................... 51

Runtime Registers ............................................................................................................................................................ 52

DMA Registers.................................................................................................................................................................. 53

Messaging Queue Registers............................................................................................................................................. 54

4.3

4.3.1

4.3.2

4.3.3

4.3.4

4.3.5

4.3.6

4.3.7

4.3.8

4.3.9

PCI CONFIGURATION REGISTERS .....................................................................................................................55

(PCIIDR; PCI:00h, LOC:00h) PCI Configuration ID Register ............................................................................................ 55

(PCICR; PCI:04h, LOC:04h) PCI Command Register ...................................................................................................... 55

(PCISR; PCI:06h, LOC:06h) PCI Status Register............................................................................................................. 56

(PCIREV; PCI:08h, LOC:08h) PCI Revision ID Register .................................................................................................. 56

(PCICCR; PCI:09-0Bh, LOC:09-0Bh) PCI Class Code Register....................................................................................... 57

(PCICLSR; PCI:0Ch, LOC:0Ch) PCI Cache Line Size Register ....................................................................................... 57

(PCILTR; PCI:0Dh, LOC:0Dh) PCI Latency Timer Register ............................................................................................. 57

(PCIHTR; PCI:0Eh, LOC:0Eh) PCI Header Type Register ............................................................................................... 57

(PCIBISTR; PCI:0Fh, LOC:0Fh) PCI Built-In Self Test (BIST) Register ........................................................................... 58

(PCIBAR0; PCI:10h, LOC:10h) PCI Base Address Register for Memory Accesses to Local, Runtime,

and DMA Registers........................................................................................................................................................... 58

(PCIBAR1; PCI:14h, LOC:14h) PCI Base Address Register for I/O Accesses to Local, Runtime, and

DMA Registers.................................................................................................................................................................. 59

(PCIBAR2; PCI:18h, LOC:18h) PCI Base Address Register for Memory Accesses to Local Address Space 0 ............... 59

(PCIBAR3; PCI:1Ch, LOC:1Ch) PCI Base Address Register for Memory Accesses to Local Address Space 1 .............. 60

(PCIBAR4; PCI:20h, LOC:20h) PCI Base Address Register ............................................................................................ 60

(PCIBAR5; PCI:24h, LOC:24h) PCI Base Address Register ............................................................................................ 60

(PCICIS; PCI:28h, LOC:28h) PCI Cardbus CIS Pointer Register ..................................................................................... 61

(PCISVID; PCI:2Ch, LOC:2Ch) PCI Subsystem Vendor ID Register................................................................................ 61

(PCISID; PCI:2Eh, LOC:2Eh) PCI Subsystem ID Register ............................................................................................... 61

(PCIERBAR; PCI:30h, LOC:30h) PCI Expansion ROM Base Register ............................................................................ 61

(PCIILR; PCI:3Ch, LOC:3Ch) PCI Interrupt Line Register ................................................................................................ 61

(PCIIPR; PCI:3Dh, LOC:3Dh) PCI Interrupt Pin Register ................................................................................................. 62

(PCIMGR; PCI:3Eh, LOC:3Eh) PCI Min_Gnt Register ..................................................................................................... 62

Page vi

Version 1.01

4.3.10

4.3.11

4.3.12

4.3.13

4.3.14

4.3.15

4.3.16

4.3.17

4.3.18

4.3.19

4.3.20

4.3.21

4.3.22

©PLX

Technology, Inc., 1997

PCI9060 Related Products

	PCI9060	PCI9060SD	PCI9060ES
Description	12O COMPATIBLE PCI BUS MASTER INTERFACE CHIP FOR ADAPTERS AND EMBEDDED SYSTEMS	12O COMPATIBLE PCI BUS MASTER INTERFACE CHIP FOR ADAPTERS AND EMBEDDED SYSTEMS	12O COMPATIBLE PCI BUS MASTER INTERFACE CHIP FOR ADAPTERS AND EMBEDDED SYSTEMS

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