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935198300112

Description
J-K Flip-Flop, HC/UH Series, 2-Func, Negative Edge Triggered, 1-Bit, Complementary Output, CMOS, PDSO16
Categorylogic    logic   
File Size93KB,15 Pages
ManufacturerNexperia
Websitehttps://www.nexperia.com
Environmental Compliance
Download Datasheet Parametric View All

935198300112 Overview

J-K Flip-Flop, HC/UH Series, 2-Func, Negative Edge Triggered, 1-Bit, Complementary Output, CMOS, PDSO16

935198300112 Parametric

Parameter NameAttribute value
Is it Rohs certified?conform to
package instructionTSSOP,
Reach Compliance Codecompliant
seriesHC/UH
JESD-30 codeR-PDSO-G16
JESD-609 codee4
length5 mm
Logic integrated circuit typeJ-K FLIP-FLOP
Humidity sensitivity level1
Number of digits1
Number of functions2
Number of terminals16
Maximum operating temperature125 °C
Minimum operating temperature-40 °C
Output polarityCOMPLEMENTARY
Package body materialPLASTIC/EPOXY
encapsulated codeTSSOP
Package shapeRECTANGULAR
Package formSMALL OUTLINE, THIN PROFILE, SHRINK PITCH
Peak Reflow Temperature (Celsius)260
propagation delay (tpd)265 ns
Certification statusNot Qualified
Maximum seat height1.1 mm
Maximum supply voltage (Vsup)6 V
Minimum supply voltage (Vsup)2 V
Nominal supply voltage (Vsup)4.5 V
surface mountYES
technologyCMOS
Temperature levelAUTOMOTIVE
Terminal surfaceNickel/Palladium/Gold (Ni/Pd/Au)
Terminal formGULL WING
Terminal pitch0.65 mm
Terminal locationDUAL
Maximum time at peak reflow temperature40
Trigger typeNEGATIVE EDGE
width4.4 mm
minfmax24 MHz
Base Number Matches1
INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT112
Dual JK flip-flop with set and reset;
negative-edge trigger
Product specification
Supersedes data of December 1990
File under Integrated Circuits, IC06
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