Philips Semiconductors
Objective specification
DECT baseband controllers
INTRODUCTION
This data sheet details the specific features of the:
PCD5090/xxx; DSP-ROM, with external ROM
PCA5097/xxx; DSP-ROM, with Field Electronically
Erasable Programmable Read Only Memory
(FEEPROM).
PCD5090; PCA5097
•
On-chip reference voltage
FEATURES
General
•
The PCx509x is designed for GAP-compliant handsets
and simple base stations
•
Embedded 80C51 microcontroller with twice the
performance of the classic architecture, up to
128 kbytes external memory or 64 kbytes FEEPROM
program memory and 3 kbytes of data memory on chip.
In addition there is 1 kbyte of on-chip data memory that
is shared with on-chip Burst Mode Logic (BML) and
DSP, the System Data RAM (SDR).
•
80C51 ports P0, P1, P2 and P3 available for interfacing
to display, keyboard, I
2
C-bus, interrupt sources and/or
external memory. External program memory is
addressable up to 128 kbytes (PCD5090/xxx and
PCA5097/xxx).
•
Portable Part (PP) and Fixed Part (FP) modes
•
TDMA frame (de)multiplexing; transmission or reception
can be programmed for any slot
•
Ciphering, scrambling, CRC checking/generation,
protected B-fields
•
Speech and data buffering space for six handsets
•
Local call and B-field loop-back
•
Two interrupt lines for BML and DSP to interrupt 80C51
•
On-chip, three-channel time-multiplexed 8-bit
Analog-to-Digital Converter (ADC) for RSSI
measurement and battery voltage measurement. One
channel available for other purposes.
•
On-chip 8-bit DAC for frequency adjustment of
13.824 MHz on-chip crystal oscillator
•
Phase error measurement and phase error correction by
hardware
•
Digital-to-Analog Converters (DACs) and ADCs for
dynamic earpiece and dynamic or electret microphone
•
On-chip supply for electret microphone
•
Very low ohmic buzzer output
•
Serial interface to external ADPCM CODEC (PCD5032)
•
IOM-2interface (Siemens registered trademark)
•
Serial interface to synthesizer for frequency
programming
•
Programmable timing of radio-control signals
•
Programmable polarity of radio-control signals
•
Easy interfacing with radio circuits, operating at other
supply voltage
•
Programmable GMSK pulse shaper
•
On-chip comparator for use as bit-slicer
•
Power-on reset
•
Low supply voltage (2.7 to 5.5 V)
•
SACMOS technology.
DSP software features
•
ADPCM encoding and decoding complying with G.721
•
Speech filters
•
Programmable gain in speech paths
•
Side tone and soft mute
•
Ringer and tone (DTMF) generator
•
Dial tone detection
•
Echo cancellation
•
Automatic gain control
•
Telephone Answering Machine (TAM) switch
•
Conference call (PCD5090/400)
•
Hands-free operation (PCD5090/311).
For each DSP software version a separate manual is
available, in which detailed information is provided on how
parameters must be set.
1996 Oct 17
2
PINNING
I/O
O
O
O
O
O
O
O
O
I
O
O
O
O
O
−
supply
supply
supply
ISP2DRF3
ISP2DRF3
ANAIOD2
ANAIOD2
ISP2DRF3
ANAIOD1
ANAIOD1
ANAIOD1
ISP2DPES
ISF2DPES
ISF2UPES
DIPP0PES
−
−
O
O
I
I
O
I
I
I
O
I/O
I
−
input
L
−
−
−
H
−
−
H
L
−
−
−
running
ISP4DRF3
H
ISP2DRF3
switch synthesizer power output
13.824 MHz reference clock for synthesizer output
negative supply voltage for RF interface level shifters
positive supply voltage for RF interface level shifters
positive supply voltage for FEEPROM program memory
switch slicer time constant output
switch receiver power output
positive input for receiver data
negative input for receiver data
enable receiver output
analog input for RSSI measurement
analog input to A/D converter
analog input for battery voltage measurement
3.456 MHz clock output for external ADPCM codec
ADPCM output or IOM data clock input/output
(ISF2UPES in PCD5090/xxx, PCA5097/xxx)
ADPCM or IOM data input
L
ISP2DRF3
L
ISP2DRF3
serial synthesizer data output
clock for serial synthesizer interface output
L
ISP2DRF3
synthesizer enable output
−
DIPP0RF3
synthesizer lock input
L
ISP2DRF3
VCO band switch output
L
ANAIOD1
GMSK modulated transmitter data output
off
ISF2DRF3
unmodulated transmitter data output
L
ISP2DRF3
switch transmitter power output
H
ISP2DRF3
enable transmitter output
H
ISP2DPES
100 Hz signal related to DECT frame timing output
H
ISP2DRF3
antenna switch 0 output
H
ISP2DRF3
antenna switch 1 output
PIN TYPE
PIN DESCRIPTION
PIN
SYMBOL
1996 Oct 17
STATE
AFTER
RESET
QFP100
LQFP100
ANT_SW1
1
99
Philips Semiconductors
ANT_SW0
2
100
CLK100
3
1
T_ENABLE
4
2
T_PWR_RMP
5
3
T_DATA
6
4
T_GMSK
7
5
DECT baseband controllers
VCO_BND_SW
8
6
SYNTH_LOCK
9
7
S_ENABLE
10
8
S_DATA
11
9
S_CLK
12
10
S_PWR
13
11
5
REF_CLK
14
12
V
SS_RF
15
13
V
DD_RF
16
14
V
DD_FEE
17
15
SLICE_CTR
18
16
R_PWR
19
17
R_DATAP
20
18
R_DATAM
21
19
R_ENABLE
22
20
RSSI_AN
23
21
VANLI
24
22
VBAT
25
23
CLK3
26
24
DCK
27
25
PCD5090; PCA5097
Objective specification
DI
28
26
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